公开(公告)号：US10740235B2

公开(公告)日：2020-08-11

申请号：US15746465

申请日：2015-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Alexandros Daglis ,  Paolo Faraboschi ,  Qiong Cai ,  Gary Gostin

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/14 ,  G06F12/0831 ,  G06F12/0811

Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

公开(公告)号：US10452498B2

公开(公告)日：2019-10-22

申请号：US14901559

申请日：2013-06-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Dale C. Morris ,  Gary Gostin ,  Russ W. Herrell ,  Andrew R. Wheeler ,  Blaine D. Gaither

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/10 ,  G06F11/20

Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.

公开(公告)号：US10355978B2

公开(公告)日：2019-07-16

申请号：US15626983

申请日：2017-06-19

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Derek Alan Sherlock ,  Gary Gostin ,  Nicholas George McDonald ,  Alan Davis ,  Darel N. Emmot ,  John Kim

IPC: H04L12/26 ,  H04L12/823 ,  H04L12/841 ,  H04L12/733 ,  H04L12/721 ,  H04L29/08

Abstract: Example implementations relate to calculating a time to live (TTL). An example implementation includes receiving a transaction request containing a first time to live (TTL) from a requester. A second TTL for a transaction response may be computed, and a transaction response containing the second TTL may be transmitted.

公开(公告)号：US10025716B2

公开(公告)日：2018-07-17

申请号：US15099984

申请日：2016-04-15

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gary Gostin ,  Craig Warner ,  John W Bockhaus

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0815 ,  G06F12/0873 ,  G06F13/16 ,  G06F12/0802 ,  G06F12/06 ,  G06F12/10

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.

公开(公告)号：US12028662B2

公开(公告)日：2024-07-02

申请号：US18154580

申请日：2023-01-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Nicholas McDonald ,  Gary Gostin ,  Alan Davis

IPC: H04Q11/00 ,  H04L49/00 ,  H04L49/15 ,  H04L49/45

CPC classification number: H04Q11/0005 ,  H04L49/15 ,  H04L49/30 ,  H04L49/45 ,  H04Q2011/0041 ,  H04Q2011/0052

Abstract: A system for hot swapping a network switch without disconnecting the network switch connectors is provided. The system disaggregates the switch faceplate network cable connectors from the internal components of the network switch so that the internal switch components may be removed from the switch without disconnecting the switch network cables.

公开(公告)号：US11637719B2

公开(公告)日：2023-04-25

申请号：US17047833

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Nicholas McDonald ,  Gary Gostin ,  Alan Davis

IPC: H04L12/28 ,  H04L12/42 ,  H04L12/403 ,  H04L41/12

Abstract: A co-packaged, multiplane network includes: an enclosure; a portion of a first network plane disposed within the enclosure and comprising a first plurality of interconnected switches; a portion of a second network plane disposed within the enclosure and comprising a second plurality of interconnected switches, the second network plane being independent of the first network plane and having the same topology as the first network plane; and a plurality of connectors, each connector being communicatively coupled to a respective port of each of the first plurality of interconnected switches and the second plurality of interconnected switches.

公开(公告)号：US10599598B1

公开(公告)日：2020-03-24

申请号：US16134499

申请日：2018-09-18

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Shawn K. Walker ,  Derek A. Sherlock ,  Gary Gostin

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/06 ,  H04L29/08

Abstract: A PCIe (Peripheral Component Interconnect Express) protocol converter for connection to a central processing unit (CPU) node having a root complex, a CPU memory fabric and CPU memory may include independent PCIe links, a fabric interface and a fabric switch connected to the fabric interface. Each of the links may include an endpoint for connection to the root complex. The fabric switch is connected to the fabric interface of each of the links and is connectable to a remote node. The fabric switch transmits writes of a single write request from the remote node across both links. Each fabric interface is to transmit an acknowledgment to the remote node in response to a write of the writes becoming observable at the CPU node hi Michael, hi Michael,.

公开(公告)号：US10540109B2

公开(公告)日：2020-01-21

申请号：US15314710

申请日：2014-09-02

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Harvey Ray ,  Gary Gostin ,  Derek Alan Sherlock ,  Gregg B. Lesartre

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G06F9/52

Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.

公开(公告)号：US10379971B2

公开(公告)日：2019-08-13

申请号：US15600408

申请日：2017-05-19

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gary Gostin ,  Erin A. Handgen

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/10 ,  G11C29/00 ,  G06F3/06 ,  G11C29/04

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

公开(公告)号：US20180367444A1

公开(公告)日：2018-12-20

申请号：US15626983

申请日：2017-06-19

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Derek Alan Sherlock ,  Gary Gostin ,  Nicholas George McDonald ,  Alan Davis ,  Darel N. Emmot ,  John Kim

IPC: H04L12/733 ,  H04L12/26

CPC classification number: H04L45/20 ,  H04L43/0864 ,  H04L43/106 ,  H04L45/26 ,  H04L47/286 ,  H04L47/32 ,  H04L67/325

Abstract: Example implementations relate to calculating a time to live (TTL). An example implementation includes receiving a transaction request containing a first time to live (TTL) from a requester. A second TTL for a transaction response may be computed, and a transaction response containing the second TTL may be transmitted.