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    Systems for introducing memristor random telegraph noise in Hopfield neural networks
    13.
    发明授权
    Systems for introducing memristor random telegraph noise in Hopfield neural networks 有权

    公开(公告)号：US11580411B2

    公开(公告)日：2023-02-14

    申请号：US16224145

    申请日：2018-12-18

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Suhas Kumar ,  Thomas Van Vaerenbergh ,  John Paul Strachan

    IPC: G06N3/10 ,  G06N3/06 ,  G11C13/00

    Abstract: Systems are provided for implementing a hardware accelerator. The hardware accelerator emulate a stochastic neural network, and includes a first memristor crossbar array, and a second memristor crossbar array. The first memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The second memristor crossbar array is coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network. The noise signals can be introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values.

    Methods and systems for highly optimized memristor write process
    14.
    发明授权
    Methods and systems for highly optimized memristor write process 有权

    公开(公告)号：US11024379B2

    公开(公告)日：2021-06-01

    申请号：US16667773

    申请日：2019-10-29

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Amit Sharma ,  John Paul Strachan ,  Suhas Kumar ,  Catherine Graves ,  Martin Foltin ,  Craig Warner

    IPC: G11C11/00 ,  G11C13/00

    Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state. Thus, utility of memristors is enhanced by realizing an optimized write process with decrease latency and improved efficiency.

    SELF-HEALING DOT-PRODUCT ENGINE
    15.
    发明申请
    SELF-HEALING DOT-PRODUCT ENGINE 审中-公开

    公开(公告)号：US20200312406A1

    公开(公告)日：2020-10-01

    申请号：US16364717

    申请日：2019-03-26

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

    IPC: G11C13/00 ,  G06F11/10 ,  G11C29/52 ,  G06N3/04

    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

    SPIKE TRAIN GENERATING CIRCUIT
    17.
    发明申请
    SPIKE TRAIN GENERATING CIRCUIT 审中-公开

    公开(公告)号：US20170324379A1

    公开(公告)日：2017-11-09

    申请号：US15657996

    申请日：2017-07-24

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Suhas Kumar

    IPC: H03B7/06 ,  H03K19/20 ,  H03B5/04

    Abstract: An oscillator circuit that includes a voltage source, a resistor, a capacitor, and a nonlinear device. The capacitor and the nonlinear device may be coupled in parallel with one another. The resistor may be coupled in series with the capacitor and the nonlinear device. The voltage source may be coupled in series with the resistor. The voltage source may supply the oscillator circuit with a direct current input signal. The nonlinear device may include an active layer coupled to a first electrode and a second electrode. In response to the direct current input signal, the oscillator circuit may output a spike train including a spike bunch.

    Systems and methods for harnessing analog noise in efficient optimization problem accelerators
    19.
    发明授权
    Systems and methods for harnessing analog noise in efficient optimization problem accelerators 有权

    公开(公告)号：US11610105B2

    公开(公告)日：2023-03-21

    申请号：US16386849

    申请日：2019-04-17

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Suhas Kumar ,  Thomas Van Vaerenbergh ,  John Paul Strachan

    IPC: G06N3/06 ,  G06N3/04 ,  G06N3/063 ,  G11C13/00 ,  H03K3/0233

    Abstract: Systems and methods are provided for implementing a hardware accelerator. The hardware accelerator emulates a neural network, and includes a memristor crossbar array, and a non-linear filter. The memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The non-linear filter is coupled to the memristor crossbar array and programmed to harness noise signals that may be present in analog circuitry of the hardware accelerator. The noise signals can be harnessed such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values. In some embodiments, the non-liner filter is implemented as a Schmidt trigger comparator.

    SELF-HEALING DOT-PRODUCT ENGINE
    20.
    发明申请
    SELF-HEALING DOT-PRODUCT ENGINE 有权

    公开(公告)号：US20210225440A1

    公开(公告)日：2021-07-22

    申请号：US17223435

    申请日：2021-04-06

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

    IPC: G11C13/00 ,  G06N3/04 ,  G11C29/52 ,  G06F11/10

    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

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