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    Selector relaxation time reduction
    2.
    发明授权
    Selector relaxation time reduction 有权

    公开(公告)号：US10026477B2

    公开(公告)日：2018-07-17

    申请号：US15329845

    申请日：2015-01-28

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Jianhua Yang ,  Ning Ge ,  John Paul Strachan ,  Gary Gibson ,  Warren Jackson

    IPC: G11C11/00 ,  G11C13/00

    Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.

    NEGATIVE DIFFERENTIAL RESISTANCE CIRCUIT ELEMENT
    3.
    发明申请
    NEGATIVE DIFFERENTIAL RESISTANCE CIRCUIT ELEMENT 有权
    负电阻电阻电路元件

    公开(公告)号：US20160351622A1

    公开(公告)日：2016-12-01

    申请号：US15114010

    申请日：2014-01-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gary Gibson ,  Warren Jackson ,  R. Stanley Williams

    IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

    CPC classification number: H01L27/2418 ,  G11C7/04 ,  G11C11/1659 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/73 ,  G11C2213/76 ,  H01L45/00 ,  H01L45/1286 ,  H01L45/145

    Abstract: A circuit component that exhibits a region of negative differential resistance includes: a first layer of material; and a second layer of material in contact with the first layer of material, the contact forming a first self-heating interface. The first self-heating interface is structured such that an electrical current flowing from the first layer of material to the second layer of material encounters an electrical impedance occurring at the first interface that is greater than any electrical impedance occurring in the first and second layers of material, wherein heating occurring at the first interface is dominated by Joule heating caused by the electrical impedance occurring at the first interface, and wherein the electrical impedance occurring at the first interface decreases with increasing temperature to induce a region of negative differential resistance.

    Abstract translation: 具有负差分电阻的区域的电路部件包括：第一层材料; 以及与所述第一材料层接触的第二材料层，所述接触件形成第一自加热界面。 第一自加热界面被构造成使得从第一材料层流向第二层材料的电流遇到在第一界面处发生的电阻抗大于在第一和第二层中发生的任何电阻抗 材料，其中在第一界面处发生的加热由由在第一界面处发生的电阻抗引起的焦耳加热主导，并且其中在第一界面处发生的电阻抗随温度升高而降低，以引起负差分电阻的区域。

    ENCODED CROSS-POINT ARRAY
    4.
    发明申请
    ENCODED CROSS-POINT ARRAY 有权
    编码交叉点阵列

    公开(公告)号：US20160343431A1

    公开(公告)日：2016-11-24

    申请号：US15113908

    申请日：2014-01-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B. Lesartre ,  Gary Gibson ,  Erik Ordentlich ,  Yoocham Jeon

    IPC: G11C13/00

    CPC classification number: G11C13/003 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/77 ,  H01L27/2463

    Abstract: A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.

    Abstract translation: 一种设备包括交叉点阵列和访问电路，以访问分别对应于编码的数据块的存储器元件的子集。 对于存储器元件的每个子集，包括子集中的第一存储器元件和该子集中的第二存储器元件的交叉点阵列的行或列还包括位于第一和第二存储器元件之间的第三存储器元件 沿着行或列的存储器元件，并且在对应于另一编码块的子集之一中。

    CROSSPOINT ARRAY DECODER
    6.
    发明申请
    CROSSPOINT ARRAY DECODER 审中-公开

    公开(公告)号：US20170287540A1

    公开(公告)日：2017-10-05

    申请号：US15507790

    申请日：2014-09-25

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Brent Buchanan ,  Amit S. Sharma ,  Gary Gibson ,  Erik Ordentlich ,  Naveen Muralimanohar

    IPC: G11C8/10 ,  G11C13/00

    CPC classification number: G11C8/10 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028

    Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, a drain voltage is applied to a drain terminal of a field effect transistor switch for a selected row in the crosspoint array associated with the selected memory element. A bulk terminal of the field effect transistor switch for the selected row can be biased with a well voltage that is independent of the drain, source, or substrate voltages. In such examples, the gate terminal of the field effect transistor switch for the selected row can be driven with a gate voltage comprising the drain voltage and the well voltage. The drain voltage, the well voltage, and the gate voltage are selected to cause the field effect transistor switch for the selected row to operate as an ohmic switch.

    NONLINEAR DIELECTRIC STACK CIRCUIT ELEMENT
    7.
    发明申请
    NONLINEAR DIELECTRIC STACK CIRCUIT ELEMENT 审中-公开
    非线性电介质电路元件

    公开(公告)号：US20160351802A1

    公开(公告)日：2016-12-01

    申请号：US15111515

    申请日：2014-01-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Warren Jackson ,  Gary Gibson ,  R. Stanley Williams ,  Jianhua Yang

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: H01L45/12 ,  G11C13/003 ,  H01L27/2418 ,  H01L45/00

    Abstract: A nonlinear dielectric stack circuit element includes a first layer of material having a first dielectric constant; a second layer of material having a second dielectric constant; and a third layer of material sandwiched between the first layer of material and the second layer of material and having a third dielectric constant. The third dielectric constant has a value less than the first dielectric constant and the second dielectric constant.

    Abstract translation: 非线性介质堆叠电路元件包括具有第一介电常数的第一材料层; 具有第二介电常数的第二材料层; 以及夹在所述第一材料层和所述第二材料层之间并具有第三介电常数的第三材料层。 第三介电常数的值小于第一介电常数和第二介电常数。

    RE-INITIALIZING MEMORY ARRAYS
    8.
    发明申请
    RE-INITIALIZING MEMORY ARRAYS 审中-公开
    重新初始化内存阵列

    公开(公告)号：US20160350023A1

    公开(公告)日：2016-12-01

    申请号：US15106444

    申请日：2014-01-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B. Lesartre ,  R. Stanley Williams ,  Gary Gibson

    IPC: G06F3/06

    CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0616 ,  G06F3/0688 ,  G06F12/0238 ,  G06F2212/1036 ,  G11C13/0033 ,  G11C16/20 ,  G11C16/3418 ,  G11C2013/0083

    Abstract: A system for re-initializing a memory array is described. The system includes a processor and a memory array communicatively coupled to the processor. The system also includes a memory manager. The memory manager includes an establish module to establish a reference state for the memory array. The reference state includes a number of target resistance values for the memory array. The memory manager includes a write module to write data to the memory array. The memory manager includes a re-initialize module to re-initialize the memory array to the established reference state.

    Abstract translation: 描述用于重新初始化存储器阵列的系统。 该系统包括处理器和通信地耦合到处理器的存储器阵列。 该系统还包括一个内存管理器。 存储器管理器包括建立模块以建立存储器阵列的参考状态。 参考状态包括存储器阵列的多个目标电阻值。 存储器管理器包括用于将数据写入存储器阵列的写入模块。 存储器管理器包括重新初始化模块以将存储器阵列重新初始化为已建立的参考状态。

    NONLINEAR MEMRISTOR DEVICES WITH THREE-LAYER SELECTORS
    10.
    发明申请
    NONLINEAR MEMRISTOR DEVICES WITH THREE-LAYER SELECTORS 有权
    具有三层选择器的非线性电容器件

    公开(公告)号：US20160254448A1

    公开(公告)日：2016-09-01

    申请号：US15032913

    申请日：2013-11-12

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Byungjoon Choi ,  Jianhua Yang ,  R. Stanley Williams ,  Gary Gibson ,  Warren Jackson

    IPC: H01L45/00

    CPC classification number: H01L45/1226 ,  H01L27/2418 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

    Abstract: A nonlinear memristor device with a three-layer selector includes a memristor in electrical series with a three-layer selector. The memristor comprises at least one electrically conducting layer and at least one electrically insulating layer. The three-layer selector comprises a three-layer structure selected from the group consisting of XN—XO—XN; XN—YO—ZN: XN—YO—XN; XO—XN—XO; XO—YN—XO; XO—YN—ZO; XO—YO—XO; XO—YO—ZO; XN—YN—ZN; and XN—YN—XN, X represents a compound-forming metal different from Y and Z.

    Abstract translation: 具有三层选择器的非线性忆阻器装置包括与三层选择器电连接的忆阻器。 忆阻器包括至少一个导电层和至少一个电绝缘层。 三层选择器包括从XN-XO-XN组成的组中选择的三层结构; XN-YO-ZN：XN-YO-XN; XO-XN-XO; XO-YN-XO; XO-YN-ZO; XO-YO-XO; XO-YO-ZO; XN-YN-ZN; 和XN-YN-XN，X表示不同于Y和Z的化合物形成金属。

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