公开(公告)号：US11268937B2

公开(公告)日：2022-03-08

申请号：US16315676

申请日：2017-07-06

Applicant: HITACHI, LTD.

Inventor： Taiichi Takezaki ,  Shuntaro Machida ,  Daisuke Ryuzaki ,  Yasuhiro Yoshimura ,  Tatsuya Nagata ,  Naoaki Yamashita

IPC: H04R19/00 ,  G01N29/24 ,  G01N29/265 ,  A61B8/00 ,  B06B1/02

Abstract: A capacitive micromachined ultrasonic transducer 111A includes: a silicon substrate 101; an insulating film 102 formed over the silicon substrate 101; a lower electrode 103; insulating films 104 and 106; a cavity 105 constituted by a void formed in a portion of the insulating film 106; an upper electrode 107; insulating films 108 and 114; and a protective film 109. In addition, the insulating film 106, upper electrode 107, insulating film 108 and insulating film 114 above the cavity 105 configure a vibration film 110, and the protective film 109 above the vibration film 110 is divided into a plurality of isolated patterns regularly arranged with a gap 115 having a constant spacing formed therebetween.

公开(公告)号：US20210043584A1

公开(公告)日：2021-02-11

申请号：US16928909

申请日：2020-07-14

Applicant: Hitachi, Ltd.

Inventor： Shuntaro Machida

IPC: H01L23/00 ,  B06B1/02 ,  B81B3/00

Abstract: Provided is a semiconductor chip, including: a semiconductor substrate; a thin film formed on the semiconductor substrate, the thin film having internal stress; and a semiconductor device formed on the semiconductor substrate that has the thin film formed thereon, wherein the semiconductor chip warps due to the internal stress of the thin film.

公开(公告)号：US10203688B2

公开(公告)日：2019-02-12

申请号：US15593747

申请日：2017-05-12

Applicant: HITACHI, LTD.

Inventor： Masaharu Kinoshita ,  Nobuyuki Sugii ,  Tomonori Sekiguchi ,  Shuntaro Machida ,  Tetsufumi Kawamura

IPC: G06F19/00 ,  G05B19/4099

Abstract: A manufacturing device inputs design information including three-dimensional structure data, generates a manufacturing process flow, and displays the manufacturing process flow on a screen for a user to check, modify, and confirm the flow based on design information and setting information. A process method includes a first process method of a direct modeling method having an FIB method and a second process method of a semiconductor manufacturing process method which is a non-FIB method. The manufacturing device generates a plurality of manufacturing process flows by a combination of cases where each of the process methods is applied to each of the regions of the three-dimensional data. The manufacturing process flow includes a process device, the process method, a control parameter value, a process time, and a total process time for each of process steps. An output unit outputs a manufacturing process flow having, for example, the shortest total process time.

公开(公告)号：US11331693B2

公开(公告)日：2022-05-17

申请号：US16361605

申请日：2019-03-22

Applicant: Hitachi, Ltd.

Inventor： Hiroaki Hasegawa ,  Kengo Imagawa ,  Shuntaro Machida ,  Taiichi Takezaki

IPC: A61B8/00 ,  B06B1/02

Abstract: Capacitors, each of which is electrically connected to a capacitor which is the cell of the CMUT mounted in a chip and is used as a DC block capacitor for protecting an amplifying circuit, are formed as many as plural aligned channels in the chip. The capacitor is an electrostatic capacitance element which is not vibrated acoustically.

公开(公告)号：US10751027B2

公开(公告)日：2020-08-25

申请号：US15325489

申请日：2015-06-19

Applicant: Hitachi, Ltd.

Inventor： Taiichi Takezaki ,  Shuntaro Machida ,  Daisuke Ryuzaki

IPC: A61B8/00 ,  G01B17/02 ,  B06B1/02 ,  G01B21/04 ,  A61B8/08 ,  G01B7/14

Abstract: Technique that enables precisely measuring cavity height and precisely grasping maximum transmission sound pressure in an ultrasonic probe is provided to the ultrasonic probe using CMUT. The ultrasonic probe according to the present invention includes plural cells each of which includes a lower electrode and an upper electrode arranged via a gap with respect to the lower electrode, and the plural cells include an ultrasonic cell the gap of which is void and which transmits/receives an ultrasonic wave and a reference cell the gap of which is filled with a conductive material. Electrostatic capacity of the ultrasonic cell and the reference cell is measured, parasitic capacity included in the measured electrostatic capacity as to the ultrasonic cell is corrected using parasitic capacity included in the measured electrostatic capacity as to the reference cell, and cavity height is calculated on the basis of the corrected electrostatic capacity of the ultrasonic cell.

公开(公告)号：US10605824B2

公开(公告)日：2020-03-31

申请号：US15763240

申请日：2016-03-18

Applicant: Hitachi, Ltd.

Inventor： Shuntaro Machida ,  Nobuyuki Sugii ,  Keiji Watanabe ,  Daisuke Ryuzaki ,  Tetsufumi Kawamura ,  Kazuki Watanabe

IPC: G01P15/08 ,  B81C99/00 ,  G01P15/125

Abstract: For the purpose of shortening the MEMS manufacturing TAT, the MEMS manufacturing method according to the present invention includes a step of extracting the first MEMS with first characteristic in a range approximate to the required characteristic from the plurality of MEMS preliminarily prepared on the main surface of the substrate, and a step of forming a second MEMS having the required characteristic by directly processing the first MEMS.