-
公开(公告)号：US09535698B2
公开(公告)日：2017-01-03
申请号：US14480522
申请日：2014-09-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Tao Huang , Qifan Zhang , Wuxian Shi , Yiqun Ge , Wen Tong
Abstract: A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.
-
公开(公告)号：US11706886B2
公开(公告)日：2023-07-18
申请号：US17487292
申请日：2021-09-28
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Weifeng Wu , Tao Huang , Li Liao , Qiang Zhan , Haiqiang Tian , Yuehua Hu
CPC classification number: H05K5/0217 , H05K5/0017
Abstract: A folding apparatus includes a first housing, a first support plate, a middle housing, a first mounting bracket, a first transmission arm, and a first rotating arm. The first mounting bracket is fixed to the first housing, the first transmission arm is rotatably connected to the middle housing, a rotation center is a first axis, and the first transmission arm is slidably connected to the first mounting bracket and slidably connected to the first support plate. The first rotating arm is rotatably connected to the middle housing, a rotation center is a second axis, the first rotating arm is rotatably connected to the first mounting bracket, and the second axis and the first axis are not collinear. The first support plate is rotatably connected to the first mounting bracket, so that the first housing and the first support plate switch between a flattened state and a folded state.
-
公开(公告)号：US20220164132A1
公开(公告)日：2022-05-26
申请号：US17669726
申请日：2022-02-11
Applicant: Huawei Technologies Co., Ltd.
IPC: G06F3/06
Abstract: A key-value (KV) storage method and apparatus, the method including receiving a write request, where the write request is associated with writing a first key and a first value, storing the first key in a first memory chip of a solid state drive (SSD), and storing the first value in a second memory chip of the SSD, where an erase count of the first memory chip is less than an erase count of the second memory chip, and creating a mapping relationship between the first key, a physical address of the first key, and a physical address of the first value, where the physical address of the first key indicates that the first key is stored in storage space of the first memory chip, and where the physical address of the first value indicates that the first value is stored in storage space of the second memory chip.
-
公开(公告)号：US11019171B2
公开(公告)日：2021-05-25
申请号：US16700109
申请日：2019-12-02
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Renchao Xie , Junfeng Xie , Hualin Zhu , Tao Huang
IPC: H04L29/08
Abstract: This disclosure provides a cache data control method and a device, applied to a first edge cache node. The method includes: receiving a data obtaining request sent from a terminal device, where the data obtaining request includes an identification of to-be-requested data; when the first edge cache node does not include the to-be-requested data, determining a target cache node that includes the to-be-requested data in an edge cache node set corresponding to the first edge cache node and a central cache node corresponding to the first edge cache node; and obtaining the to-be-requested data from the target cache node. This disclosure is intended to improve efficiency of feeding back data information to the terminal device.
-
公开(公告)号：US10511494B2
公开(公告)日：2019-12-17
申请号：US15644340
申请日：2017-07-07
Applicant: Huawei Technologies Co., Ltd.
Inventor： Hualin Wan , Xijun Xue , Tao Huang
IPC: H04L12/24 , G06Q20/06 , H04L29/06 , H04L12/851
Abstract: A network control method relates to the communications field, includes receiving, by a controller, a packet forwarded by a forwarder, detecting, by the controller, a status of a virtual currency identifier of the packet, querying, by the controller according to a user identifier in the packet, whether the user has permission to improve service quality when the status of the virtual currency identifier of the packet indicates that a user is willing to pay virtual currency to raise a network priority, and raising, by the controller, the network priority of the user, starting charging, and sending a network priority of the user to the forwarder when the user has the permission to improve the service quality such that the forwarder forwards a packet of the user according to the network priority of the user.
-
Patent Agency Ranking
16.发明授权公开(公告)号：US09928074B2
公开(公告)日：2018-03-27
申请号：US14480035
申请日：2014-09-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yiqun Ge , Wuxian Shi , Qifan Zhang , Tao Huang , Wen Tong
CPC classification number: G06F9/3871 , G06F9/3836 , G06F9/3885 , G06F13/4204 , G06F13/4282
Abstract: Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time (referred to as very long instruction word) and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.
-
公开(公告)号：US20170264693A1
公开(公告)日：2017-09-14
申请号：US15607080
申请日：2017-05-26
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xijun Xue , Tao Huang , Yingtao Li
CPC classification number: H04L67/125 , G06F3/0325 , G06F19/3418 , G06F21/32 , H04L12/28 , H04W72/0473
Abstract: The present invention relates to the computer field, and specifically, to a method and an apparatus for coordinating body devices for communication. The method includes: obtaining, by a mobile personal station, an identifier of a body device, and a location parameter and an ambient parameter that are of a user that carries the body device; obtaining, according to the identifier of the body device, a communication mode supported by the body device; obtaining, according to the identifier of the body device, a communication mode supported by the body device; determining, a networking mode of the body device according to the scenario and the communication mode supported by the body device; and establishing, a connection to the body device according to the networking mode.
-
公开(公告)号：US09762224B2
公开(公告)日：2017-09-12
申请号：US15057509
申请日：2016-03-01
Applicant: Huawei Technologies Co., Ltd.
Inventor： Tao Huang
CPC classification number: H03K5/24 , H03K3/0375
Abstract: A timing prediction circuit and method which relate to the field of circuit technologies and may be used to predict a timing margin of a to-be-predicted digital circuit, which are used to resolve a problem that a large quantity of devices are used to predict a probability that a timing error occurs in a to-be-predicted digital circuit. The timing prediction circuit includes a combinational logic circuit, a delay circuit, a sampling circuit, and a control circuit, where the sampling circuit includes N samplers, and an input end of each sampler is separately connected to an output end of the combinational logic circuit using the delay circuit, and an output end of each sampler is connected to an input end of the control circuit, where N is an integer equal, and N≧2. The present invention can be used to predict a timing margin of a to-be-predicted digital circuit.
-
19.发明授权System and method for an asynchronous processor with a hierarchical token system 有权具有分层令牌系统的异步处理器的系统和方法公开(公告)号：US09495316B2
公开(公告)日：2016-11-15
申请号：US14480330
申请日：2014-09-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yiqun Ge , Wuxian Shi , Qifan Zhang , Tao Huang , Wen Tong
IPC: G06F13/38
CPC classification number: G06F13/385
Abstract: Embodiments are provided for an asynchronous processor with a Hierarchical Token System. The asynchronous processor includes a set of primary processing units configured to gate and pass a set of tokens in a predefined order of a primary token system. The asynchronous processor further includes a set of secondary units configured to gate and pass a second set of tokens in a second predefined order of a secondary token system. The set of tokens of the primary token system includes a token consumed in the set of primary processing units and designated for triggering the secondary token system in the set of secondary units.
Abstract translation: 为具有分层令牌系统的异步处理器提供实施例。 异步处理器包括一组主处理单元，其被配置为按照主要令牌系统的预定义顺序来选择和传递一组令牌。 异步处理器还包括一组辅助单元，其被配置为以辅助令牌系统的第二预定义顺序选通和传递第二组令牌。 主令牌系统的令牌集合包括在主处理单元组中消耗的令牌，并被指定用于触发该次要单元组中的辅助令牌系统。
-
公开(公告)号：US20160261257A1
公开(公告)日：2016-09-08
申请号：US15057509
申请日：2016-03-01
Applicant: Huawei Technologies Co., Ltd.
Inventor： Tao Huang
IPC: H03K5/24
CPC classification number: H03K5/24 , H03K3/0375
Abstract: A timing prediction circuit and method which relate to the field of circuit technologies and may be used to predict a timing margin of a to-be-predicted digital circuit, which are used to resolve a problem that a large quantity of devices are used to predict a probability that a timing error occurs in a to-be-predicted digital circuit. The timing prediction circuit includes a combinational logic circuit, a delay circuit, a sampling circuit, and a control circuit, where the sampling circuit includes N samplers, and an input end of each sampler is separately connected to an output end of the combinational logic circuit using the delay circuit, and an output end of each sampler is connected to an input end of the control circuit, where N is an integer equal, and N≧2. The present invention can be used to predict a timing margin of a to-be-predicted digital circuit.
Abstract translation: 一种与电路技术领域有关的定时预测电路和方法，可用于预测待预测数字电路的定时裕度，其用于解决大量设备用于预测的问题 在待预测的数字电路中发生定时误差的概率。 定时预测电路包括组合逻辑电路，延迟电路，采样电路和控制电路，其中采样电路包括N个采样器，并且每个采样器的输入端分别连接到组合逻辑电路的输出端 使用延迟电路，并且每个采样器的输出端连接到控制电路的输入端，其中N是等于的整数，并且N≥2。 本发明可以用于预测待预测的数字电路的定时裕度。
-
-
-
-
-
-
-
-
-
Search Results
59
records
(took 0.027 seconds)
