公开(公告)号：US20250047649A1

公开(公告)日：2025-02-06

申请号：US18822799

申请日：2024-09-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Wen Tong

IPC: H04L9/40 ,  G06N3/045 ,  G06N5/04

Abstract: Some embodiments of the present disclosure provide certification for the handling of an inference request that is transmitted to a DNN hosted on a remote computing system. Output data, received responsive to the inference request, may be certified as being appropriately generated by the DNN, rather than being tampered with or generated by a malicious DNN. Output data from the DNN may be also certified as appropriately corresponding to input data included in the inference request. Linear block coding may be used on transmissions to guard against eavesdropping and tampering. Through the use of a certification DNN, a degree of comfort may be gained that given output data appropriately corresponds to input data included in a given inference request. Furthermore, known patterns inherent in DNN outputs may be used to establish the integrity of received out

公开(公告)号：US09928074B2

公开(公告)日：2018-03-27

申请号：US14480035

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/38 ,  G06F13/42

CPC classification number: G06F9/3871 ,  G06F9/3836 ,  G06F9/3885 ,  G06F13/4204 ,  G06F13/4282

Abstract: Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time (referred to as very long instruction word) and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.

公开(公告)号：US09495316B2

公开(公告)日：2016-11-15

申请号：US14480330

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: Embodiments are provided for an asynchronous processor with a Hierarchical Token System. The asynchronous processor includes a set of primary processing units configured to gate and pass a set of tokens in a predefined order of a primary token system. The asynchronous processor further includes a set of secondary units configured to gate and pass a second set of tokens in a second predefined order of a secondary token system. The set of tokens of the primary token system includes a token consumed in the set of primary processing units and designated for triggering the secondary token system in the set of secondary units.

Abstract translation: 为具有分层令牌系统的异步处理器提供实施例。 异步处理器包括一组主处理单元，其被配置为按照主要令牌系统的预定义顺序来选择和传递一组令牌。 异步处理器还包括一组辅助单元，其被配置为以辅助令牌系统的第二预定义顺序选通和传递第二组令牌。 主令牌系统的令牌集合包括在主处理单元组中消耗的令牌，并被指定用于触发该次要单元组中的辅助令牌系统。

公开(公告)号：US20250045599A1

公开(公告)日：2025-02-06

申请号：US18884948

申请日：2024-09-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Adam Christian Cavatassi ,  Yiqun Ge ,  Wen Tong ,  Wuxian Shi

IPC: G06N3/0985

Abstract: Some embodiments of the present application provide a forward-propagation-only (FP-only) method of training a DNN model. Such methods result in a trained DNN model whose performance comparable to a DNN model trained using bidirectional training methods. The FP-only method for training a DNN model may operate without employing the known chain rule. The chain rule is employed when computing gradients for a backward propagation in a bidirectional method. The FP-only method may allow for the computations and updates to the parameters for each layer of the DNN model to be performed in parallel. The FP-only methods for training a DNN model use stochastic gradient descent and the FP-only method for training a DNN model still involves computing gradients. However, the FP-only methods of training a DNN model allow for computing of gradients without the chain rule.

公开(公告)号：US10980030B2

公开(公告)日：2021-04-13

申请号：US16562045

申请日：2019-09-05

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Wen Tong

IPC: G06F9/44 ,  H04W72/04 ,  H04B7/10 ,  G06N3/08 ,  G06N3/04 ,  H04L5/00

Abstract: A polarization stream architecture is described. A transmitter may implement a reverse polarization stream to shape a first source signal in a first signal space to a first target signal in a second signal space. The reverse polarization stream is implemented as a cascade of reverse polarization steps. Each reverse polarization step includes a shuffle function, a split function, a scaling function and an offset function. Machine-learning techniques may be used to implement the scaling function and the offset function. A receiver may implement a polarization stream to recover the source signal.

公开(公告)号：US20160291980A1

公开(公告)日：2016-10-06

申请号：US14676461

申请日：2015-04-01

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yiqun Ge ,  Wuxian Shi

IPC: G06F9/38 ,  G06F9/355

CPC classification number: G06F9/3814 ,  G06F9/30105 ,  G06F9/3557 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3871 ,  G06F9/3885

Abstract: A superscalar processor, for out of order self-timed execution, comprising a plurality of independent self-timed function units, having corresponding instruction queues for holding instructions to be executed by the function unit. The processor further comprising an instruction dispatcher configured for inputting instructions in program counter order; and determining an appropriate function unit for execution of the instruction and a resource management unit configured for monitoring the function units and signaling availability of the appropriate function unit, wherein the dispatcher only dispatches the instruction to the appropriate function unit in response to the availability signal from the resource management unit.

Abstract translation: 一种超标量处理器，用于无序自定时执行，包括多个独立的自定时功能单元，具有用于保持由功能单元执行的指令的相应指令队列。 所述处理器还包括配置成以程序计数器顺序输入指令的指令分配器; 以及确定用于执行所述指令的适当功能单元和被配置用于监视所述功能单元和所述适当功能单元的信令可用性的资源管理单元，其中所述调度员仅响应于来自所述功能单元的可用性信号将所述指令发送到所述适当的功能单元 资源管理单元。

公开(公告)号：US11463980B2

公开(公告)日：2022-10-04

申请号：US16795137

申请日：2020-02-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wuxian Shi ,  Yiqun Ge ,  Wen Tong

IPC: H04W64/00 ,  H04W16/28 ,  H04W76/11 ,  H04W4/02

Abstract: Methods and systems are described which use a sensing system in cooperation with a wireless communication system. Coordinate information (which may be from the sensing system, from an electronic device, or from a network-side device) and signal-related information (which may be from the wireless system) are associated with each other. The associated information may be used for wireless communication management, such as beam management operations, among others.

公开(公告)号：US10372458B2

公开(公告)日：2019-08-06

申请号：US14676461

申请日：2015-04-01

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yiqun Ge ,  Wuxian Shi

IPC: G06F9/38 ,  G06F9/355 ,  G06F9/30

Abstract: A superscalar processor, for out of order self-timed execution, comprising a plurality of independent self-timed function units, having corresponding instruction queues for holding instructions to be executed by the function unit. The processor further comprising an instruction dispatcher configured for inputting instructions in program counter order; and determining an appropriate function unit for execution of the instruction and a resource management unit configured for monitoring the function units and signaling availability of the appropriate function unit, wherein the dispatcher only dispatches the instruction to the appropriate function unit in response to the availability signal from the resource management unit.

公开(公告)号：US10042641B2

公开(公告)日：2018-08-07

申请号：US14480573

申请日：2014-09-08

Applicant: Huawei Technologies Co. Ltd

Inventor： Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Tao Huang ,  Wen Tong

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F1/08 ,  G06F1/10 ,  G06F9/50

Abstract: An asynchronous processing system comprising an asynchronous scalar processor and an asynchronous vector processor coupled to the scalar processor. The asynchronous scalar processor is configured to perform processing functions on input data and to output instructions. The asynchronous vector processor is configured to perform processing functions in response to a very long instruction word (VLIW) received from the scalar processor. The VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.

公开(公告)号：US09846581B2

公开(公告)日：2017-12-19

申请号：US14480556

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tao Huang ,  Yiqun Ge ,  Qifan Zhang ,  Wuxian Shi ,  Wen Tong

IPC: G06F9/38 ,  G06F15/80 ,  G06F15/82 ,  G06F9/30 ,  G06F1/08 ,  G06F1/10 ,  G06F9/50

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.