公开(公告)号：US20110127606A1

公开(公告)日：2011-06-02

申请号：US12592619

申请日：2009-11-30

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingpeng Guan ,  Yeeheng Lee ,  John Chen

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingpeng Guan ,  Yeeheng Lee ,  John Chen

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0705 ,  H01L29/0634 ,  H01L29/66901 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： This invention discloses configurations and methods to manufacture lateral power device including a super junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

摘要翻译： 本发明公开了制造横向功率器件的结构和方法，该器件包括在漏极与栅极之间形成的具有雪崩钳位二极管的超结结构。 横向超结结构降低了导通电阻，而结构增强（包括雪崩钳位二极管和N缓冲区）增加了衬底和漏极之间的击穿电压，并改善了非钳位感应开关（UIS）性能。

公开(公告)号：US20160005809A1

公开(公告)日：2016-01-07

申请号：US14298537

申请日：2014-06-06

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/06 ,  H01L21/761

CPC分类号： H01L29/0634 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/6609 ,  H01L29/861

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

公开(公告)号：US09231050B1

公开(公告)日：2016-01-05

申请号：US14298537

申请日：2014-06-06

申请人： Madhur Bobde ,  Lingping Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingping Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L21/761

CPC分类号： H01L29/0634 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/6609 ,  H01L29/861

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

公开(公告)号：US20130260522A1

公开(公告)日：2013-10-03

申请号：US13900162

申请日：2013-05-22

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7802 ,  H01L29/7811

摘要： A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.

摘要翻译： 交错列超结半导体器件可以包括具有一个或多个器件单元的单元区域。 单元区域中的一个或多个器件单元包括被配置为用作漏极的半导体衬底和形成在衬底上的半导体层。 第一掺杂柱可以在半导体层中形成为第一深度，并且第二掺杂柱可以形成在半导体层中至第二深度。 第一个深度大于第二个深度。 第一和第二列掺杂有相同第二导电类型的掺杂剂并且沿着半导体层的厚度的一部分延伸并且由半导体层的一部分分离。

公开(公告)号：US20130049102A1

公开(公告)日：2013-02-28

申请号：US13199381

申请日：2011-08-25

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises a buried field ring regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried field ring regions to function as a charge supply path.

摘要翻译： 本发明公开了一种形成在半导体衬底中的半导体功率器件，包括在轻掺杂区域顶部附近的半导体衬底的顶表面附近的高掺杂区域。 半导体功率器件还包括设置在半导体衬底的顶表面附近的体区，源区和栅极以及设置在半导体衬底的底表面处的漏极。 半导体功率器件还包括开口到高掺杂区域的源沟槽，填充有与顶表面附近的源区电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域具有相反导电性的掺杂剂的掩埋场环区域。 在替代实施例中，半导体功率器件还包括围绕源极沟槽的侧壁的掺杂区域，并掺杂有相同导电类型的掩埋场环区域的掺杂剂，用作电荷供应路径。

公开(公告)号：US08373208B2

公开(公告)日：2013-02-12

申请号：US12799810

申请日：2010-04-30

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L21/8232

CPC分类号： H01L29/808 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66696 ,  H01L29/66901 ,  H01L29/7817 ,  H01L29/7821

摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

摘要翻译： 横向超结JFET由负载在N +衬底上的P表面层上的堆叠的交替P型和N型半导体层形成。 N +漏极柱向下延伸穿过超结结构和P-epi以连接到N +衬底以使器件成为底部漏极器件。 N +源极柱和P +栅极柱延伸穿过超级结，但在P-epi层处停止。 栅极 - 漏极雪崩钳位二极管从P +栅极底部通过P-epi到N +漏极衬底形成。

公开(公告)号：US10103240B2

公开(公告)日：2018-10-16

申请号：US13763675

申请日：2013-02-10

申请人： Madhur Bobde ,  Lingpeng Guann ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guann ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66

摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

公开(公告)号：US20170117386A9

公开(公告)日：2017-04-27

申请号：US13763675

申请日：2013-02-10

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66

CPC分类号： H01L29/66484 ,  H01L29/0634 ,  H01L29/42316 ,  H01L29/66901 ,  H01L29/66909 ,  H01L29/78 ,  H01L29/808

摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

公开(公告)号：US08900949B2

公开(公告)日：2014-12-02

申请号：US13900162

申请日：2013-05-22

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7802 ,  H01L29/7811

摘要： A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.

摘要翻译： 交错列超结半导体器件可以包括具有一个或多个器件单元的单元区域。 单元区域中的一个或多个器件单元包括被配置为用作漏极的半导体衬底和形成在衬底上的半导体层。 第一掺杂柱可以在半导体层中形成为第一深度，并且第二掺杂柱可以形成在半导体层中至第二深度。 第一个深度大于第二个深度。 第一和第二列掺杂有相同第二导电类型的掺杂剂并且沿着半导体层的厚度的一部分延伸并且由半导体层的一部分分离。

公开(公告)号：US08829640B2

公开(公告)日：2014-09-09

申请号：US13065824

申请日：2011-03-29

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/02 ,  H01L29/06

CPC分类号： H01L29/0634 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/6609 ,  H01L29/861

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

摘要翻译： 本发明公开了一种半导体功率器件，其设置在半导体衬底中，并具有有源电池区域和边缘终端区域的边缘终端区域，其中边缘终端区域包括具有交替导电类型的掺杂半导体柱的超结构结构，其中电荷不平衡 掺杂的半导体柱在边缘终端中产生鞍形电场。