STAGGERED COLUMN SUPERJUNCTION
    4.
    发明申请

    公开(公告)号:US20130260522A1

    公开(公告)日:2013-10-03

    申请号:US13900162

    申请日:2013-05-22

    IPC分类号: H01L29/66

    摘要: A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.

    摘要翻译: 交错列超结半导体器件可以包括具有一个或多个器件单元的单元区域。 单元区域中的一个或多个器件单元包括被配置为用作漏极的半导体衬底和形成在衬底上的半导体层。 第一掺杂柱可以在半导体层中形成为第一深度,并且第二掺杂柱可以形成在半导体层中至第二深度。 第一个深度大于第二个深度。 第一和第二列掺杂有相同第二导电类型的掺杂剂并且沿着半导体层的厚度的一部分延伸并且由半导体层的一部分分离。

    Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path
    5.
    发明申请
    Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path 有权
    埋地场环形场效应晶体管(BUF-FET)与注入孔供电路径的电池集成

    公开(公告)号:US20130049102A1

    公开(公告)日:2013-02-28

    申请号:US13199381

    申请日:2011-08-25

    IPC分类号: H01L29/78 H01L21/336

    摘要: This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises a buried field ring regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried field ring regions to function as a charge supply path.

    摘要翻译: 本发明公开了一种形成在半导体衬底中的半导体功率器件,包括在轻掺杂区域顶部附近的半导体衬底的顶表面附近的高掺杂区域。 半导体功率器件还包括设置在半导体衬底的顶表面附近的体区,源区和栅极以及设置在半导体衬底的底表面处的漏极。 半导体功率器件还包括开口到高掺杂区域的源沟槽,填充有与顶表面附近的源区电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域具有相反导电性的掺杂剂的掩埋场环区域。 在替代实施例中,半导体功率器件还包括围绕源极沟槽的侧壁的掺杂区域,并掺杂有相同导电类型的掩埋场环区域的掺杂剂,用作电荷供应路径。