公开(公告)号：US20080318406A1

公开(公告)日：2008-12-25

申请号：US12194202

申请日：2008-08-19

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L21/3205

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.

摘要翻译： 在分闸式非易失存储器件及其制造方法中， 辅助层图案设置在半导体衬底的源极区域上。 由于源区域由于存在辅助层图案而垂直延伸，因此可以增加浮置栅极与源区域和辅助层图案重叠的区域的面积。 因此，形成在源极和浮置栅极之间的电容器的电容增加，使得非易失性存储器件可以在低电压电平下执行编程/擦除操作。

公开(公告)号：US07351636B2

公开(公告)日：2008-04-01

申请号：US11138702

申请日：2005-05-26

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7885

摘要： A method of forming a split-gate non-volatile memory cell can include forming first and second adjacent floating gates self-aligned to a field oxide region therebetween. An oxide layer is formed covering the first and second adjacent floating gates and the field oxide region, the oxide layer electrically isolates the first and second adjacent floating gates from one another. A control gate is formed on the oxide layer on the first and second adjacent floating gates. Related devices are also disclosed.

摘要翻译： 形成分闸非易失性存储单元的方法可以包括形成与其之间的场氧化物区域自对准的第一和第二相邻浮置栅极。 形成覆盖第一和第二相邻浮动栅极和场氧化物区域的氧化物层，氧化物层将第一和第二相邻浮栅彼此电隔离。 控制栅极形成在第一和第二相邻浮动栅极上的氧化物层上。 还公开了相关设备。

公开(公告)号：US07586146B2

公开(公告)日：2009-09-08

申请号：US11837361

申请日：2007-08-10

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han

IPC分类号： H01L29/788

CPC分类号： H01L29/7885 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.

摘要翻译： 在一个实施例中，半导体器件包括具有第一结区域和第二结区域的半导体衬底。 绝缘浮栅设置在基板上。 浮置栅极至少部分地与第一结区重叠。 在浮动门上设置绝缘程序门。 程序门具有弯曲的上表面。 半导体器件还包括布置在衬底上并与浮动栅极相邻的绝缘擦除栅极。 擦除栅极部分地与第二结区重叠。

公开(公告)号：US07271061B2

公开(公告)日：2007-09-18

申请号：US11187424

申请日：2005-07-21

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han

IPC分类号： H01L21/336

CPC分类号： H01L29/7885 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.

摘要翻译： 在一个实施例中，半导体器件包括具有第一结区域和第二结区域的半导体衬底。 绝缘浮栅设置在基板上。 浮置栅极至少部分地与第一结区重叠。 在浮动门上设置绝缘程序门。 程序门具有弯曲的上表面。 半导体器件还包括布置在衬底上并与浮动栅极相邻的绝缘擦除栅极。 擦除栅极部分地与第二结区重叠。

公开(公告)号：US20060199359A1

公开(公告)日：2006-09-07

申请号：US11415466

申请日：2006-05-01

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/792

摘要： In a local-length nitride SONOS device and a method for forming the same, a local-length nitride floating gate structure is provided for mitigating or preventing lateral electron migration in the nitride floating gate. The structure includes a thin gate oxide, which leads to devices having a lower threshold voltage. In addition, the local-length nitride layer is self-aligned, which prevents nitride misalignment, and therefore leads to reduced threshold voltage variation among the devices.

摘要翻译： 在本地长度的氮化物SONOS器件及其形成方法中，提供局部长度的氮化物浮栅结构，用于减轻或防止氮化物浮栅中的横向电子迁移。 该结构包括薄栅极氧化物，其导致具有较低阈值电压的器件。 此外，局部长度的氮化物层是自对准的，这防止氮化物不对准，并且因此导致器件之间的阈值电压变化降低。

公开(公告)号：US07148110B2

公开(公告)日：2006-12-12

申请号：US11415466

申请日：2006-05-01

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

IPC分类号： H02L21/336

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/792

摘要： In a local-length nitride SONOS device and a method for forming the same, a local-length nitride floating gate structure is provided for mitigating or preventing lateral electron migration in the nitride floating gate. The structure includes a thin gate oxide, which leads to devices having a lower threshold voltage. In addition, the local-length nitride layer is self-aligned, which prevents nitride misalignment, and therefore leads to reduced threshold voltage variation among the devices.

摘要翻译： 在本地长度的氮化物SONOS器件及其形成方法中，提供局部长度的氮化物浮栅结构，用于减轻或防止氮化物浮栅中的横向电子迁移。 该结构包括薄栅极氧化物，其导致具有较低阈值电压的器件。 此外，局部长度的氮化物层是自对准的，这防止氮化物不对准，并且因此导致器件之间的阈值电压变化降低。

公开(公告)号：US07064378B2

公开(公告)日：2006-06-20

申请号：US10832948

申请日：2004-04-27

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7923

摘要： In a local-length nitride SONOS device and a method for forming the same, a local-length nitride floating gate structure is provided for mitigating or preventing lateral electron migration in the nitride floating gate. The structure includes a thin gate oxide, which leads to devices having a lower threshold voltage. In addition, the local-length nitride layer is self-aligned, which prevents nitride misalignment, and therefore leads to reduced threshold voltage variation among the devices.

公开(公告)号：US20050059209A1

公开(公告)日：2005-03-17

申请号：US10832948

申请日：2004-04-27

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Yong-Tae Kim

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7923

摘要： In a local-length nitride SONOS device and a method for forming the same, a local-length nitride floating gate structure is provided for mitigating or preventing lateral electron migration in the nitride floating gate. The structure includes a thin gate oxide, which leads to devices having a lower threshold voltage. In addition, the local-length nitride layer is self-aligned, which prevents nitride misalignment, and therefore leads to reduced threshold voltage variation among the devices.

摘要翻译： 在本地长度的氮化物SONOS器件及其形成方法中，提供局部长度的氮化物浮栅结构，用于减轻或防止氮化物浮栅中的横向电子迁移。 该结构包括薄栅极氧化物，其导致具有较低阈值电压的器件。 此外，局部长度的氮化物层是自对准的，这防止氮化物不对准，并且因此导致器件之间的阈值电压变化降低。

公开(公告)号：US20110175153A1

公开(公告)日：2011-07-21

申请号：US13075778

申请日：2011-03-30

申请人： Sang-Woo Kang ,  Jeong-Uk Han ,  Yong-Tae Kim ,  Seung-Beom Yoon

发明人： Sang-Woo Kang ,  Jeong-Uk Han ,  Yong-Tae Kim ,  Seung-Beom Yoon

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L27/105 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.

摘要翻译： 半导体器件包括具有垂直栅电极的晶体管。 在晶体管结构中，半导体图案具有面向横向的第一和第二侧以及纵向方向上的第三和第四侧。 栅极图案被布置成与半导体图案的第一和第二侧相邻。 杂质图案直接接触半导体图案的第三面和第四面。 栅极绝缘图案插入在栅极图案和半导体图案之间。

公开(公告)号：US07936003B2

公开(公告)日：2011-05-03

申请号：US11344560

申请日：2006-01-31

申请人： Sang-Woo Kang ,  Jeong-Uk Han ,  Yong-Tae Kim ,  Seung-Beom Yoon

发明人： Sang-Woo Kang ,  Jeong-Uk Han ,  Yong-Tae Kim ,  Seung-Beom Yoon

IPC分类号： H01L29/788

CPC分类号： H01L29/785 ,  H01L27/105 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.

摘要翻译： 半导体器件包括具有垂直栅电极的晶体管。 在晶体管结构中，半导体图案具有面向横向的第一和第二侧以及纵向方向上的第三和第四侧。 栅极图案被布置成与半导体图案的第一和第二侧相邻。 杂质图案直接接触半导体图案的第三面和第四面。 栅极绝缘图案插入在栅极图案和半导体图案之间。