公开(公告)号：US06311203B1

公开(公告)日：2001-10-30

申请号：US09203373

申请日：1998-12-02

申请人： Yasushi Wada ,  Shuji Murakami

发明人： Yasushi Wada ,  Shuji Murakami

IPC分类号： G06F752

CPC分类号： H03H17/06 ,  G06F7/523

摘要： A multiplication device for performing a multiplication operation on a multiplicand X and two fixed coefficients C1 and C2 where C1>C2. The multiplication device comprises a multiplier for multiplying multiplicand X and the average CA of the two fixed coefficients C1 and C2; a shift register for obtaining a sum of the multiplicand X data after being shifted up according to a position of a “1” bit in bit data where the bit data is the remainder coefficient obtained by subtracting average CA from fixed coefficient C1; and a selector for selecting a product obtained for one of the fixed coefficients C1 and C2. When the fixed coefficient C1 is selected, the selector outputs the sum of the product returned by the multiplier and the accumulated value obtained by the shift register; when fixed coefficient C2 is selected, the selector outputs the difference of the product returned by the multiplier minus the accumulated value obtained by the shift register. A fixed coefficient FIR digital filter having a plurality of multiplication devices above-mentioned is also disclosed.

摘要翻译： 用于对被乘数X和两个固定系数C1和C2执行乘法运算的乘法装置，其中C1> C2。 乘法装置包括用于将被乘数X与两个固定系数C1和C2的平均CA相乘的乘法器; 移位寄存器，用于根据比特数据中的“1”位的位置向上移位被乘数X数据，其中比特数据是通过从固定系数C1减去平均CA而获得的余数系数; 以及选择器，用于选择为固定系数C1和C2之一获得的乘积。 当选择固定系数C1时，选择器输出由乘法器返回的乘积和由移位寄存器获得的累加值之和; 当选择固定系数C2时，选择器输出由乘数返回的乘积的差值减去由移位寄存器获得的累加值。 还公开了具有上述多个乘法装置的固定系数FIR数字滤波器。

公开(公告)号：US06834376B2

公开(公告)日：2004-12-21

申请号：US10212768

申请日：2002-08-07

申请人： Yasushi Wada

发明人： Yasushi Wada

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A logic optimization device refers to hierarchical circuit-design descriptions representing multiple layers of an integrated circuit, and decides whether or not each output terminal at each lower layer is connected with its upper layer. If an output terminal at a lower layer has been decided to be unconnected with its upper layer, the logic optimization device deletes from the hierarchical circuit-design descriptions an information part describing the output terminal, and deletes from the hierarchical circuit-design descriptions an information part describing an element at the lower layer connected with the deleted output terminal, thereby producing a gate-level net-list of an integrated circuit without ineffectual elements.

摘要翻译： 逻辑优化装置是指表示集成电路的多层的分层电路设计描述，并且判定每个下层的每个输出端是否与其上层连接。 如果下层的输出端子决定与其上层不连接，则逻辑优化装置从分层电路设计描述中删除描述输出端子的信息部分，并从分层电路设计描述中删除信息 描述与删除的输出端子连接的下层的元件的部分，由此产生集成电路的门级网络列表，而没有无效元件。

公开(公告)号：US06453449B1

公开(公告)日：2002-09-17

申请号：US09360641

申请日：1999-07-26

申请人： Yasushi Wada

发明人： Yasushi Wada

IPC分类号： G06F1750

CPC分类号： G06F17/504

摘要： There is described a means of shortening of the time required for verification by a formal logic verification system which compares details of a circuit represented in the form of a register transfer level (RTL) description with details of the circuit represented in the form of a gate level netlist. Logical equivalence between an RTL description and a gate level netlist obtained through logical compilation of the RTL descriptions is verified. In a case where a plurality of blocks having the same function are included in the circuit, one of a plurality of descriptions that are included in the netlist and relate to the function is compared with the RTL description relating to the functional blocks (comparison {circle around (1)}). If one of the descriptions of the netlist has already been verified, a plurality of descriptions included in the netlist are compared with the description that is taken as the first reference description.

摘要翻译： 描述了通过形式逻辑验证系统来缩短验证所需的时间的手段，该系统比较以寄存器传送级（RTL）描述形式表示的电路的细节与以门的形式表示的电路的细节 级别网表。 验证通过RTL描述的逻辑编译获得的RTL描述和门级网表之间的逻辑等价性。 在具有相同功能的多个块包括在电路中的情况下，将包括在网表中并涉及功能的多个描述之一与与功能块相关的RTL描述进行比较（比较{circle around（1）}）。 如果网表的描述之一已经被验证，则将包括在网表中的多个描述与作为第一参考描述的描述进行比较。

公开(公告)号：US4390520A

公开(公告)日：1983-06-28

申请号：US248912

申请日：1981-03-30

申请人： Hidetaka Nagai ,  Yasushi Wada ,  Ichiro Kobayashi ,  Mitsuru Tamada ,  Keiichi Ushiyama ,  Toshiyuki Yamamoto

发明人： Hidetaka Nagai ,  Yasushi Wada ,  Ichiro Kobayashi ,  Mitsuru Tamada ,  Keiichi Ushiyama ,  Toshiyuki Yamamoto

IPC分类号： A61K31/405 ,  A61K9/70 ,  A61K47/14 ,  A61L15/58 ,  A61F13/00 ,  A61L15/00

CPC分类号： A61K9/7061 ,  A61L15/58

摘要： An antiphlogistic analgesic adhesive which comprisesa flexible substrate andan indomethacin containing pressure-sensitive adhesive layer closely contacting said flexible substrate, wherein said pressure-sensitive adhesive layer comprises a mixture of(a) indomethacin,(b) a copolymer of (i) an alkyl acrylate having 4 to 11 carbon atoms in the alkyl moiety and (ii) a functional monomer having a functional group in the molecule thereof and/or a vinyl monomer, which has pressure-sensitive adhesive properties at room temperature, and(c) an absorption accelerating assistant which maintains said indomethacin in a solubilized state in said copolymer and has skin diffusibility.

摘要翻译： 一种消炎镇痛粘合剂，其包含柔性基底和与所述柔性基底紧密接触的含有吲哚美辛的压敏粘合剂层，其中所述压敏粘合剂层包含（a）吲哚美辛，（b）（i） 烷基部分中具有4〜11个碳原子的丙烯酸烷基酯和（ⅱ）在其分子中具有官能团的官能单体和/或在室温下具有压敏粘合性能的乙烯基单体，和（c） 吸收加速助剂，其将所述吲哚美辛维持在所述共聚物中的溶解状态，并具有皮肤扩散性。

公开(公告)号：US20100296870A1

公开(公告)日：2010-11-25

申请号：US12675531

申请日：2008-08-25

申请人： Naoki Ono ,  Hiroaki Sakamoto ,  Kazuhiro Hirao ,  Toshinobu Kakita ,  Yasushi Wada ,  Yoshihito Fujii ,  Tsuneo Onodera

发明人： Naoki Ono ,  Hiroaki Sakamoto ,  Kazuhiro Hirao ,  Toshinobu Kakita ,  Yasushi Wada ,  Yoshihito Fujii ,  Tsuneo Onodera

IPC分类号： E02B13/00 ,  F16L9/00

CPC分类号： A01G25/06

摘要： A subirrigation system 10 includes a water-impervious member 16, and keeps water content in soil of a cultivated land 200 in a proper state for growing a plant. The water-impervious member 16 is formed into an upper opening vessel shape, and has a water reserving function. Water is fed to an inner portion of the water-impervious member 16 from a water tank 12 via a feed water pipe 14, whereby a soil portion 26 in a gravitational water state is formed. A water level 28 of the gravitational water within the water-impervious member 16 is properly controlled to a desired water level by a water level controller 18 provided in the feed water pipe 14. The gravitational water within the water-impervious member 16 controlled to the desired water level is appropriately sucked up to the soil in an upper layer in accordance with a capillary phenomenon. Accordingly, a soil portion 30 in a capillary water state having proper water content is formed in the cultivated land 200.

摘要翻译： 子灌溉系统10包括不透水构件16，并且在适当的状态下将耕地200的土壤中的含水量保持在植物生长中。 防水构件16形成为上开口容器形状，并具有储水功能。 水通过给水管14从水箱12供给到不透水构件16的内部，由此形成重力水状态的土壤部分26。 不透水构件16内的重力水的水位28被设置在给水管14中的水位控制器18适当地控制到期望的水位。防水构件16内的重力控制到 根据毛细管现象，期望的水位被适当吸入上层的土壤。 因此，在耕地200中形成具有适当含水量的毛细水分状态的土壤部分30。

公开(公告)号：US06720811B2

公开(公告)日：2004-04-13

申请号：US10193251

申请日：2002-07-12

申请人： Minobu Yazawa ,  Shinichi Nakagawa ,  Yasushi Wada

发明人： Minobu Yazawa ,  Shinichi Nakagawa ,  Yasushi Wada

IPC分类号： H03L700

CPC分类号： H03K5/135 ,  G06F1/10 ,  H03K5/133 ,  H03K2005/00078

摘要： A semiconductor device includes a delay amount measuring unit, multiple delay sections and a correction signal generating unit. The delay amount measuring unit for measures an actual delay amount corresponding to a specified delay amount by supplying a clock signal with a known period to multiple 1-ns-delay strings with a preassigned delay amount, and by detecting phase variations of the clock signal by the 1-ns-delay strings. The delay sections includes a delay string capable of freely adjusting a connection number of its delay elements. The correction signal generating unit generates a correction signal for enabling each of the delay sections to correct the connection number of the delay strings such that each delay section has a desired delay amount, in accordance with the actual delay amount corresponding to the specified delay amount and measured by the delay measuring unit.

摘要翻译： 半导体器件包括延迟量测量单元，多个延迟部分和校正信号生成单元。 延迟量测量单元，用于通过向具有预分配的延迟量的多个1-ns延迟串提供具有已知周期的时钟信号，并且通过检测时钟信号的相位变化来检测相应于指定延迟量的实际延迟量， 1 ns延迟字符串。 延迟部分包括能够自由地调节其延迟元件的连接数量的延迟串。 校正信号生成单元根据与规定的延迟量对应的实际延迟量，生成用于使每个延迟部分能够校正延迟串的连接数，使得每个延迟部分具有期望的延迟量的校正信号，以及 由延迟测量单元测量。

公开(公告)号：US20060183664A1

公开(公告)日：2006-08-17

申请号：US10496851

申请日：2002-12-13

申请人： Toshiaki Takizawa ,  Masaki Tamiya ,  Naohiro Saito ,  Toru Kanke ,  Jiro Matsumoto ,  Yasushi Wada ,  Junichi Kawagoe ,  William Ferrell ,  John Lockhart

发明人： Toshiaki Takizawa ,  Masaki Tamiya ,  Naohiro Saito ,  Toru Kanke ,  Jiro Matsumoto ,  Yasushi Wada ,  Junichi Kawagoe ,  William Ferrell ,  John Lockhart

IPC分类号： A61K38/54

CPC分类号： A61K45/06 ,  A61K31/00 ,  Y02A50/423 ,  A61K2300/00

摘要： The present invention provides a pharmaceutical composition by a novel action mechanism without serious side effects for delayed hypersensitivity and a screening method of the same. The invention also provides a novel assay method of inhibitors/suppressive agents of PAR-2. The invention relates to a pharmaceutical composition for delayed hypersensitivity containing one or two or more active ingredients selected from the group consisting of inhibitors of PAR-2 and suppressive agents of PAR-2 gene expression and a pharmaceutically acceptable carrier, and to a method for screening active ingredients for pharmaceutical composition for delayed hypersensitivity by contacting a subject substance with cells expressing PAR-2 and by determining expression or activity of PAR-2. The invention also relates to a method for detecting or quantifying actions of the subject substance for PAR-2 using cells expressing PAR-2 in a culture containing inositol.

摘要翻译： 本发明通过新颖的作用机理提供药物组合物，对迟发性超敏反应没有严重的副作用及其筛选方法。 本发明还提供了PAR-2抑制剂/抑制剂的新型测定方法。 本发明涉及一种用于延迟超敏反应的药物组合物，其含有选自PAR-2的抑制剂和PAR-2基因表达的抑制剂的一种或两种以上活性成分和药学上可接受的载体，以及筛选方法 通过使受试物质与表达PAR-2的细胞接触并通过测定PAR-2的表达或活性来延迟超敏反应的药物组合物的活性成分。 本发明还涉及使用含有肌醇的培养物中表达PAR-2的细胞检测或定量PAR-2的物质的作用的方法。

公开(公告)号：US07423009B2

公开(公告)日：2008-09-09

申请号：US10673380

申请日：2003-09-30

申请人： Takashi Nakagawa ,  Hiroyuki Ishiwata ,  Toshiaki Takizawa ,  Toru Kanke ,  Yasushi Wada ,  Junichi Kawagoe

发明人： Takashi Nakagawa ,  Hiroyuki Ishiwata ,  Toshiaki Takizawa ,  Toru Kanke ,  Yasushi Wada ,  Junichi Kawagoe

IPC分类号： A61K38/00 ,  A61K38/43 ,  A61K38/48

CPC分类号： A61K38/4846 ,  A61K38/08 ,  A61K38/482 ,  A61K38/4826 ,  G01N33/6893 ,  G01N2500/00 ,  G01N2800/347

摘要： The present invention relates to a composition for prevention and treatment of kidney diseases comprising one or more effective component(s) of a PAR-2 activating agent which is able to activate PAR-2 and a pharmaceutically acceptable carrier. The present invention further relates to a method for prevention and treatment of kidney diseases comprising administration of a composition for prevention and treatment of kidney diseases containing a PAR-2 activating agent which is able to activate PAR-2 to patients suffering from kidney diseases, and also relates to the use of a PAR-2 activating agent which is able to activate PAR-2 for the manufacture of a composition for prevention and treatment of kidney diseases. The present invention furthermore relates to a method for screening an effective ingredient for prevention and treatment of kidney diseases comprising screening of the activating action of the test substance to PAR-2.

摘要翻译： 本发明涉及一种用于预防和治疗肾脏疾病的组合物，其包含能够激活PAR-2的PAR-2活化剂的一种或多种有效成分和药学上可接受的载体。 本发明还涉及一种用于预防和治疗肾脏疾病的方法，其包括给予含有能够使患有肾脏疾病的患者PAR-2的PAR-2激活剂的肾脏疾病的预防和治疗组合物，以及 还涉及能够激活PAR-2用于制备用于预防和治疗肾脏疾病的组合物的PAR-2活化剂的用途。 本发明还涉及筛选用于预防和治疗肾脏疾病的有效成分的方法，其包括将测试物质的活化作用筛选到PAR-2。

公开(公告)号：US06490710B1

公开(公告)日：2002-12-03

申请号：US09630412

申请日：2000-08-01

申请人： Yasushi Wada

发明人： Yasushi Wada

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： After a logic verification is made in a low-hierarchical block, a logic verification is made in a high-hierarchical block circuit in a state that the low-hierarchical block is not the subject of comparison. Even if the number of input ports in the low-hierarchical block increases due to a change of the circuit, logical equivalence of the high-hierarchical circuit is verified by using equivalence information of the input ports.

摘要翻译： 在低级别块进行逻辑验证之后，在低分级块不是比较对象的状态下，在高层次块电路中进行逻辑验证。 即使由于电路的变化而导致的低级块的输入端口的数量增加，也可以通过使用输入端口的等价信息来验证高层次电路的逻辑等价。