公开(公告)号：US20200312406A1

公开(公告)日：2020-10-01

申请号：US16364717

申请日：2019-03-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

IPC: G11C13/00 ,  G06F11/10 ,  G11C29/52 ,  G06N3/04

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

公开(公告)号：US10312943B2

公开(公告)日：2019-06-04

申请号：US15468619

申请日：2017-03-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Craig Warner ,  Martin Foltin ,  Chris Michael Brueggen ,  Brian S. Birk ,  Harvey Ray

IPC: H03M13/00 ,  H03M13/29 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

公开(公告)号：US10025716B2

公开(公告)日：2018-07-17

申请号：US15099984

申请日：2016-04-15

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gary Gostin ,  Craig Warner ,  John W Bockhaus

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0815 ,  G06F12/0873 ,  G06F13/16 ,  G06F12/0802 ,  G06F12/06 ,  G06F12/10

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.

公开(公告)号：US20210225440A1

公开(公告)日：2021-07-22

申请号：US17223435

申请日：2021-04-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

IPC: G11C13/00 ,  G06N3/04 ,  G11C29/52 ,  G06F11/10

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

公开(公告)号：US10984860B2

公开(公告)日：2021-04-20

申请号：US16364717

申请日：2019-03-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

IPC: G11C13/00 ,  G06F11/10 ,  G06N3/04 ,  G11C29/52

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

公开(公告)号：US10474389B2

公开(公告)日：2019-11-12

申请号：US15201981

申请日：2016-07-05

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Brian S. Birk ,  Joseph F. Orth ,  Harvey Ray ,  Craig Warner

IPC: G06F3/06

Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.

公开(公告)号：US20180011660A1

公开(公告)日：2018-01-11

申请号：US15201981

申请日：2016-07-05

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Brian S. Birk ,  Joseph F. Orth ,  Harvey Ray ,  Craig Warner

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0673 ,  G06F3/0679

Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.