公开(公告)号：US20230421451A1

公开(公告)日：2023-12-28

申请号：US18464680

申请日：2023-09-11

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Montgomery C. McGraw ,  Dwight D. Riley

IPC: H04L41/12 ,  H04L49/00 ,  H04L49/10

CPC classification number: H04L41/12 ,  H04L49/70 ,  H04L49/10 ,  H04L49/356

Abstract: An apparatus in a first computing device is provided. During operation, the apparatus can present, to a processor of the first computing device, a virtual interface switch (VIS) coupled to an interface port of the processor. The apparatus can present to the processor that a target device, which is reachable via a remote apparatus of a second computing device, is coupled to the VIS. The apparatuses can be coupled via at least a first fabric and a second fabric. A respective fabric may facilitate communication based on a fabric switching protocol. The apparatus can obtain a set of packets, which can be issued from the interface port via the VIS and directed to the target device. The apparatus can then forward, to the remote apparatus, a first subset of the set of packets via the first fabric and a second subset of the set of packets via the second fabric.

公开(公告)号：US20220060382A1

公开(公告)日：2022-02-24

申请号：US16997473

申请日：2020-08-19

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Montgomery C. McGraw ,  Dwight D. Riley

IPC: H04L12/24 ,  H04L12/933 ,  H04L12/931

Abstract: An apparatus in a first computing device is provided. During operation, the apparatus can present, to a processor of the first computing device, a virtual interface switch (VIS) coupled to an interface port of the processor. The apparatus can present to the processor that a target device, which is reachable via a remote apparatus of a second computing device, is coupled to the VIS. The apparatuses can be coupled via at least a first fabric and a second fabric. A respective fabric may facilitate communication based on a fabric switching protocol. The apparatus can obtain a set of packets, which can be issued from the interface port via the VIS and directed to the target device. The apparatus can then forward, to the remote apparatus, a first subset of the set of packets via the first fabric and a second subset of the set of packets via the second fabric.

公开(公告)号：US20190069436A1

公开(公告)日：2019-02-28

申请号：US15684658

申请日：2017-08-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Norton ,  Dwight D. Riley

IPC: H05K7/14 ,  G06F21/86 ,  G07C9/00

Abstract: Example implementations relate to a locking mechanism of a module of a data center. In some examples, a controller may comprise a processing resource and a memory resource storing machine-readable instructions to receive a request to unlock a locking mechanism of a module of a data center, authenticate a user associated with the request to unlock the locking mechanism by comparing credentials included with the unlock request with permissions associated with the user, and unlock the locking mechanism of the module of the data center in response to the credentials having proper permissions.

公开(公告)号：US10157017B2

公开(公告)日：2018-12-18

申请号：US15500072

申请日：2015-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dwight D. Riley ,  Joseph E. Foster ,  Thierry Fevrier

IPC: G06F3/06 ,  G06F13/16 ,  G06F11/14 ,  G06F11/20 ,  G06F13/28

Abstract: According to an example, data may be replicated using a dual-port nonvolatile dual in-line memory module (NVDIMM). A processor may request, through a first port of the dual-port NVDIMM, to store data to universal memory of the dual-port NVDIMM and to commit the data to remote storage according to a high-availability storage capability of the dual-port NVDIMM. The process may then receive a notification from the dual-port NVDIMM that the data has been transparently committed to the remote storage through a second port of the dual-port NVDIMM.

公开(公告)号：US20180004422A1

公开(公告)日：2018-01-04

申请号：US15540237

申请日：2015-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dwight D. Riley ,  Joseph E. Foster ,  Thierry Fevrier

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/1081 ,  G06F13/28 ,  G06F11/20

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0679 ,  G06F11/2023 ,  G06F12/1081 ,  G06F13/1684 ,  G06F13/28 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/656

Abstract: According to an example, a dual-port non-volatile dual in-line memory module (NVDIMM) includes a first port to provide a central processing unit (CPU) with access to universal memory of the dual-port NVDIMM and a second port to provide an external NVDIMM manager circuit with access to the universal memory of the dual-port NVDIMM. Accordingly, a media controller of the dual-port NVDIMM may store data received from the CPU through the first port in the universal memory, control dual-port settings received from the CPU, and transmit the stored data to the NVDIMM manager circuit through the second port of the dual-port NVDIMM.

公开(公告)号：US20240256679A1

公开(公告)日：2024-08-01

申请号：US18161934

申请日：2023-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Shiva R. Dasari ,  Dwight D. Riley

IPC: G06F21/60 ,  G06F21/79

CPC classification number: G06F21/602 ,  G06F21/79

Abstract: In some examples, a security chip for an electronic device includes a nonvolatile memory to store a collection of encryption keys for encrypting information to produce encrypted information. The security chip includes a discrete secure erase hardware logic and is separate from a collection of device processors of the electronic device. The discrete secure erase hardware logic receives an erase indication indicating a request to erase the encrypted information. In response to the erase indication, the discrete secure erase hardware logic erases the collection of encryption keys in the nonvolatile memory, and activates an output indication to cause activation of an erase indicator at the electronic device.

公开(公告)号：US20230132853A1

公开(公告)日：2023-05-04

申请号：US17452790

申请日：2021-10-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dwight D. Riley ,  Scott P. Faasse

IPC: G06F13/10 ,  G06F21/82

Abstract: A supervisory service of a node that includes a smart input/output (I/O) peripheral is extended into a cloud operator domain that is associated with the smart I/O peripheral. The supervisory service determines a state of a ready state indicator that is provided by the smart I/O peripheral. Based on the state, the supervisory service performs at least one of regulating an availability of an instance of an application operating environment of the node or determining whether the smart I/O peripheral is ready to be configured by the supervisory service.

公开(公告)号：US10649680B2

公开(公告)日：2020-05-12

申请号：US15540237

申请日：2015-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dwight D. Riley ,  Joseph E. Foster ,  Thierry Fevrier

IPC: G06F3/06 ,  G06F12/1081 ,  G06F13/16 ,  G06F11/20 ,  G06F13/28

Abstract: According to an example, a dual-port non-volatile dual in-line memory module (NVDIMM) includes a first port to provide a central processing unit (CPU) with access to universal memory of the dual-port NVDIMM and a second port to provide an external NVDIMM manager circuit with access to the universal memory of the dual-port NVDIMM. Accordingly, a media controller of the dual-port NVDIMM may store data received from the CPU through the first port in the universal memory, control dual-port settings received from the CPU, and transmit the stored data to the NVDIMM manager circuit through the second port of the dual-port NVDIMM.