公开(公告)号：US5598365A

公开(公告)日：1997-01-28

申请号：US493609

申请日：1995-06-22

申请人： Masakazu Shoji

发明人： Masakazu Shoji

IPC分类号： G11C17/18 ,  G11C11/56 ,  G11C16/04 ,  G11C17/12 ,  G11C17/00

CPC分类号： G11C17/12 ,  G11C11/56 ,  G11C11/5692 ,  G11C16/24 ,  G11C2211/5617 ,  G11C7/1006 ,  G11C7/18

摘要： A system and method for the storage of digital information wherein data that would normally be represented by multiple bits of information is effectively stored at single memory site within a ROM. This is accomplished by employing a multiple bit-line memory architecture, in conjunction with a data decoder. With this arrangement it is possible to store, at a single memory site, information that would have required up to .left brkt-top.log.sub.2 (n(n-1)/2)+1).right brkt-top. individual memory sites in a conventional ROM (where n is the number independent of bit-lines connected to an individual memory element in the invention). The invention is particularly well-suited to what would be considered relatively low-speed data retrieval systems, such as those adapted to provide audio and/or video to a user on a real time basis.

摘要翻译： 用于存储数字信息的系统和方法，其中通常由多位信息表示的数据被有效地存储在ROM内的单个存储器位置。 这通过结合数据解码器采用多位线存储器架构来实现。 通过这种布置，可以在单个存储器站点存储在常规ROM中需要高达+539log2（n（n-1）/ 2）+1）+538个别存储器位置的信息（其中n 是与本发明中的单个存储元件连接的位线无关的数字）。 本发明特别适合于将被认为是相对低速的数据检索系统，例如那些适合于实时地向用户提供音频和/或视频的系统。

公开(公告)号：US4782253A

公开(公告)日：1988-11-01

申请号：US99702

申请日：1987-09-21

申请人： Masakazu Shoji

发明人： Masakazu Shoji

IPC分类号： H01L27/02 ,  H03K5/151 ,  H03K5/05 ,  H03K5/01 ,  H03K5/06 ,  H03K5/12

CPC分类号： H03K5/151 ,  H01L27/0207

摘要： Integrated circuit chips with two (or more) multi-element logic paths--suffering from signal skew operation because of semiconductor processing variations--can be made to exhibit substantially reduced skew by designing the elements such that the sum of the pull-up delays in one logic path is approximately equal to the sum of the pull-up delays in the other logic path (or in each of the other logic paths) and such that the sum of all the delays (pull-down plus pull-up) in one path is substantially equal to the sum of all the delays in (each of) the other(s)--all in response to an input signal transition (low to high, high to low, or both) applied to each path.

摘要翻译： 具有两个（或多个）多元件逻辑路径的集成电路芯片 - 由于半导体处理变化而遭受信号偏移操作 - 可以通过设计元件使得这些元件中的上拉延迟之和显现出显着降低的偏移 逻辑路径近似等于另一逻辑路径（或其他逻辑路径中的每一个）中的上拉延迟的总和，并且使得一条路径中的所有延迟（下拉加上拉）之和 基本上等于其他（的）每一个的响应于每个路径的输入信号转换（从低到高，高到低或两者）的所有延迟的总和。

公开(公告)号：US4572972A

公开(公告)日：1986-02-25

申请号：US458770

申请日：1983-01-18

申请人： Masakazu Shoji

发明人： Masakazu Shoji

IPC分类号： H01L23/528 ,  H01L27/092 ,  H03K17/687

CPC分类号： H01L27/092 ,  H01L23/5286 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/3011

摘要： An integrated circuit chip with a preferred ground structure and including only pull-down transistors (on-chip) is operated by means of an off-chip pull-up transistor arrangement for precharging the data bus to logic high. The arrangement exhibits relatively low noise characteristics allowing relatively high frequency operation without generating noise voltages which exceed FET threshold voltages.

摘要翻译： 具有优选接地结构并且仅包括下拉晶体管（片上）的集成电路芯片通过用于将数据总线预充电为逻辑高的片外上拉晶体管布置来操作。 该装置显示相对低的噪声特性，允许相对高频率的操作，而不产生超过FET阈值电压的噪声电压。

公开(公告)号：US4430583A

公开(公告)日：1984-02-07

申请号：US316560

申请日：1981-10-30

申请人： Masakazu Shoji

发明人： Masakazu Shoji

IPC分类号： H01L29/78 ,  H01L27/088 ,  H03K17/04 ,  H03K19/0948 ,  H03K19/017 ,  H03K19/09 ,  H03K19/094

CPC分类号： H01L27/088 ,  H03K19/0948

摘要： In an IGFET circuit having a long string of more than two transistors connected in series between an output terminal and a power supply terminal where the load capacitance across the output terminal is on the same order of magnitude as the parasitic capacitances at the junctures of the transistors in the string, the switching-delay is not significantly reduced by uniformly increasing the conduction channel widths of the transistors in the string. However, according to the present invention, a substantial reduction in the switching delay of such a circuit may be obtained by scaling the conduction channel widths of the transistors in the string so as to provide a positive gradient in conduction channel widths along the string in the direction from the output terminal to the power supply terminal. It is particularly advantageous to use exponential scaling of the conduction channel widths. The present invention is also applicable to transistor strings which include one or more groups of parallel connected transistors.

摘要翻译： 在具有串联连接在输出端子和电源端子之间的多于两个晶体管的长串串联的IGFET电路中，跨输出端子的负载电容与晶体管的接合处的寄生电容相同数量级 在串中，通过均匀地增加串中的晶体管的导通通道宽度，开关延迟不会显着降低。 然而，根据本发明，可以通过缩放串中的晶体管的导通通道宽度来获得这种电路的开关延迟的显着减小，以便沿着串中的串提供导通通道宽度的正梯度 方向从输出端子到电源端子。 使用传导通道宽度的指数缩放是特别有利的。 本发明还可应用于包括一组或多组并联的晶体管的晶体管串。

公开(公告)号：US4403287A

公开(公告)日：1983-09-06

申请号：US295857

申请日：1981-08-24

申请人： Donald E. Blahut ,  Jonathan A. Fields ,  Victor K. Huang ,  Charles M. Lee ,  Masakazu Shoji

发明人： Donald E. Blahut ,  Jonathan A. Fields ,  Victor K. Huang ,  Charles M. Lee ,  Masakazu Shoji

IPC分类号： G06F11/28 ,  G06F11/22 ,  G06F11/267 ,  G06F11/36 ,  G06F15/78 ,  G06F11/00

CPC分类号： G06F11/3648 ,  G06F11/2236

摘要： A single-chip processor architecture is disclosed which permits the registers and control latches of the processor to be easily accessed without using instructions to achieve such access. The architecture provides for an internal access (IA) function which is enabled by applying an IA Request signal to an IA terminal of the processor. During the IA function, program execution in the processor is suspended and the registers and control latches may be accessed as if they were storage locations in a random access memory. After the IA function is enabled, the address of a register or control latch selected for access is applied to the Address/Data port of the processor, and an IA Control Code specifying the strobing of the Address/Data port is applied to the Status terminals of the processor. After strobing of the address, a second IA Control Code specifying either reading or writing of the selected register or control latch is applied to the Status terminals. If the second Control Code specifies reading, the contents of the selected register or control latch is provided at the Address/Data port. If the second Control Code specifies writing, data received at the Address/Data port is stored in the selected register. The IA function facilitates program development in the processor because it provides an efficient means for observing the internal machine states and register contents of the processor. Functional testing of the processor is also facilitated because the IA function increases the availability of the internal nodes of the processor chip for the application of test signals and for the observation of circuit responses.

摘要翻译： 公开了一种单芯片处理器架构，其允许容易地访问处理器的寄存器和控制锁存器，而无需使用指令来实现这种访问。 该架构提供内部访问（IA）功能，其通过将IA请求信号应用于处理器的IA终端来实现。 在IA功能期间，处理器中的程序执行被暂停，并且可以访问寄存器和控制锁存器，就像它们是随机存取存储器中的存储单元一样。 在启用IA功能之后，选择用于访问的寄存器或控制锁存器的地址被应用于处理器的地址/数据端口，并且将指定地址/数据端口选通的IA控制代码应用于状态端子 的处理器。 在选通地址之后，将第二个IA控制代码指定为选择的寄存器或控制锁存器的读取或写入状态终端。 如果第二个控制代码指定读取，则在地址/数据端口提供所选寄存器或控制锁存器的内容。 如果第二个控制代码指定写入，则在地址/数据端口接收的数据存储在所选择的寄存器中。 IA功能有助于处理器中的程序开发，因为它提供了一种观察内部机器状态和注册处理器内容的有效手段。 处理器的功能测试也是便利的，因为IA功能增加了处理器芯片的内部节点的可用性，以应用测试信号和观察电路响应。

公开(公告)号：US4320409A

公开(公告)日：1982-03-16

申请号：US145611

申请日：1980-05-01

申请人： Masakazu Shoji

发明人： Masakazu Shoji

IPC分类号： H01L27/092 ,  H01L27/02

CPC分类号： H01L27/0921

摘要： A CMOS integrated circuit structure having an improved guardband configuration for the prevention of parasitic SCR latchup. Included with each guardband is a pair of field reducing surface regions of the opposite conductivity type to that of the guardband and situated one on each side of the guardband adjacent thereto. The field reducing regions which are electrically connected to each other serve to reduce any electric fields in the bulk region underlying the guardband thereby significantly improving the effectiveness of the guardband for collecting minority carriers in the bulk region to provide greater protection from latchup.

摘要翻译： 一种CMOS集成电路结构，具有改进的防护带配置，用于防止寄生SCR闭锁。 每个防护带包括一对与防护带相反的导电类型的场减小表面区域，并且位于与其相邻的防护带的每一侧上。 彼此电连接的场减小区域用于减少保护带下方的体区域中的任何电场，从而显着提高用于收集大块区域中的少数载流子的保护带的有效性，从而提供更大的保护以防闭锁。

公开(公告)号：US09079546B2

公开(公告)日：2015-07-14

申请号：US13820363

申请日：2010-12-14

申请人： Masakazu Shoji

发明人： Masakazu Shoji

IPC分类号： B60R16/02 ,  H04B1/08

CPC分类号： B60R16/02 ,  H04B1/082

摘要： A main body chassis 101 in which a navigation side connector 109 is positioned and fixed, and a display part chassis 203 in which an LCD side connector 205 is positioned and fixed are positioned by abutting a pair of positioning bosses 116 of each of positioning parts 115a and 115b against both-shoulder portions 214 of each of positioning protruding pieces 211a and 211b, and are secured with screws; whether the navigation side connector 109 and the LCD side connector 205 are connected or not can be confirmed by presence or absence of a fitting between a fitting pawl 118 of the outer wall surface and a fitting hole 213.

摘要翻译： 其中定位和固定导航侧连接器109的主体机架101以及定位和固定LCD侧连接器205的显示部分机架203通过邻接每个定位部分115a的一对定位凸台116来定位 和115b抵靠每个定位突出片211a和211b的两肩部214，并用螺钉固定; 导航侧连接器109和LCD侧连接器205是否连接可以通过外壁表面的配合爪118和装配孔213之间的配合的存在或不存在来确认。

公开(公告)号：US20130154361A1

公开(公告)日：2013-06-20

申请号：US13820363

申请日：2010-12-14

申请人： Masakazu Shoji

发明人： Masakazu Shoji

IPC分类号： B60R16/02

CPC分类号： B60R16/02 ,  H04B1/082

摘要： A main body chassis 101 in which a navigation side connector 109 is positioned and fixed, and a display part chassis 203 in which an LCD side connector 205 is positioned and fixed are positioned by abutting a pair of positioning bosses 116 of each of positioning parts 115a and 115b against both-shoulder portions 214 of each of positioning protruding pieces 211a and 211b, and are secured with screws; whether the navigation side connector 109 and the LCD side connector 205 are connected or not can be confirmed by presence or absence of a fitting between a fitting pawl 118 of the outer wall surface and a fitting hole 213.

摘要翻译： 其中定位和固定导航侧连接器109的主体机架101以及定位和固定LCD侧连接器205的显示部分机架203通过邻接每个定位部分115a的一对定位凸台116来定位 和115b抵靠每个定位突出片211a和211b的两肩部214，并用螺钉固定; 导航侧连接器109和LCD侧连接器205是否连接可以通过外壁表面的配合爪118和装配孔213之间的配合的存在或不存在来确认。

公开(公告)号：US07811654B2

公开(公告)日：2010-10-12

申请号：US11666820

申请日：2005-09-13

申请人： Masakazu Shoji ,  Keishi Fujii

发明人： Masakazu Shoji ,  Keishi Fujii

IPC分类号： B32B3/00 ,  B32B3/28 ,  B32B3/30

CPC分类号： B29C45/2708 ,  Y10T428/15 ,  Y10T428/24479 ,  Y10T428/2457

摘要： In gate-processed moldings fabricated by cutting off a gate 5 formed on resin moldings 1 during molding of the resin moldings 1, an introducing section 4 for cutting off the gate is formed thereon.

摘要翻译： 在树脂成型体1成型时切断形成在树脂成形体1上的浇口5而制作的浇口加工成形体中，形成切断浇口的导入部4。

公开(公告)号：US5418178A

公开(公告)日：1995-05-23

申请号：US261622

申请日：1994-06-17

申请人： Masakazu Shoji

发明人： Masakazu Shoji

IPC分类号： H01L21/8246

CPC分类号： H01L27/11273 ,  Y10S148/088

摘要： A method for fabricating read-only memory ("ROM") devices utilizing junction field-effect transistors ("JFETs") having a conductive channel orthogonally oriented with respect to the surface of the semiconductor material composing the JFET. A fixed-position ion beam is employed to create this narrow gate channel, which extends between the JFET's source and drain contact. Employing such JFETs as basic memory sites within a semiconductor ROM circuit allows for an architecture that conforms to a minimum lattice structure layout. In addition, the resulting ROM offers high speed access of data. Although JFETs have not been utilized as the transistor of choice within ROMs because of their seemingly inferior performance when compared to MOSFETs, the invention provides a novel architecture which significantly enhances the practicality of the JFET as a memory device.

摘要翻译： 一种用于制造具有相对于构成JFET的半导体材料的表面正交取向的导电沟道的结型场效应晶体管（“JFET”）的制造只读存储器（“ROM”）器件的方法。 使用固定位置离子束来产生该窄栅极通道，其在JFET的源极和漏极接触之间延伸。 将这样的JFET作为半导体ROM电路中的基本存储器位置允许符合最小格子结构布局的架构。 此外，所得到的ROM提供数据的高速访问。 尽管JFET与MOSFET相比，由于它们的性能看起来性能较差，虽然JFET尚未被用作ROM内选择的晶体管，但是本发明提供了一种新颖的架构，其显着提高了JFET作为存储器件的实用性。