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公开(公告)号：US08639905B2
公开(公告)日：2014-01-28
申请号：US13614313
申请日：2012-09-13
IPC分类号： G06F12/02
CPC分类号： G06F11/1641 , G06F11/1683
摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.
摘要翻译： 其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。 微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入 两次，并且第一次和第二次的写入数据被相互整理。
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公开(公告)号：US08589612B2
公开(公告)日：2013-11-19
申请号：US13106788
申请日：2011-05-12
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F11/1641 , G06F2201/845
摘要： A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.
摘要翻译： 提供一种缩短CPU的待机时间并提高从性能模式（并行操作）切换到安全模式（主/检测器操作）时的CPU处理效率的计算机系统。 在一个计算机系统中，包括：至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器，用于相互比较CPU的输出，分别由CPU执行相互不同的处理的性能模式之间进行切换，以提高CPU的性能和执行相同处理的安全模式，并将比较器的结果进行比较 检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。
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公开(公告)号：US08291188B2
公开(公告)日：2012-10-16
申请号：US12706938
申请日：2010-02-17
IPC分类号： G06F12/12
CPC分类号： G06F11/1641 , G06F11/1683
摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.
摘要翻译： 其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。 微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入 两次，并且第一次和第二次的写入数据被相互整理。
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公开(公告)号：US20050040978A1
公开(公告)日：2005-02-24
申请号：US10912542
申请日：2004-08-06
申请人： Yuichiro Morita , Kohei Sakurai , Nobuyasu Kanekawa , Masatoshi Hoshino , Hiromichi Yamada , Kotaro Shimamura , Satoshi Tanaka , Naoki Yada
发明人： Yuichiro Morita , Kohei Sakurai , Nobuyasu Kanekawa , Masatoshi Hoshino , Hiromichi Yamada , Kotaro Shimamura , Satoshi Tanaka , Naoki Yada
CPC分类号： H03M1/1225
摘要： In an A/D converter and a microcontroller including the same, the number of selection patterns of analog input channels is increased for each A/D conversion and the A/D conversion is conducted using an A/D converter having only fundamental functions without imposing load onto a CPU. The A/D converter or a DMA transfer device includes an A/D conversion table including one or more entries. Each entry includes enable bits for setting whether or not an A/D conversion is executed for the respective analog input channels and a plurality of count number bits for setting a number of executions of the A/D conversion.
摘要翻译： 在A / D转换器和包含该A / D转换器的微控制器中，对于每个A / D转换，模拟输入通道的选择模式的数量增加，并且使用仅具有基本功能的A / D转换器进行A / D转换，而不施加 加载到CPU上 A / D转换器或DMA传输装置包括包括一个或多个条目的A / D转换表。 每个条目包括用于设置是否对各个模拟输入通道执行A / D转换的使能位以及用于设置A / D转换执行次数的多个计数号位。
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15.发明授权Communications system, and information processing device and control device incorporating said communications system 失效通信系统，以及包含所述通信系统的信息处理设备和控制设备公开(公告)号：US07765269B2
公开(公告)日：2010-07-27
申请号：US10980837
申请日：2004-11-04
申请人： Nobuyasu Kanekawa , Hiromichi Yamada , Kohei Sakurai , Kotaro Shimamura , Yuichiro Morita , Satoshi Tanaka
发明人： Nobuyasu Kanekawa , Hiromichi Yamada , Kohei Sakurai , Kotaro Shimamura , Yuichiro Morita , Satoshi Tanaka
IPC分类号： G06F15/16
CPC分类号： G06F13/4217
摘要： This invention provides communications systems that enable broadcasting while making use of the simplicity of the prior art and also provides control devices and information processing systems incorporating the communications system. In this invention, chip-select signals are provided for transmitting (TXCSi) and receiving (RXCSi) independently as well as for individual chips as in the prior art. That is, a group of signals indicating whether or not a slave node is selected as the node to transmit signals to a master node and the direction of communications are output from the master node to the slave node.
摘要翻译： 本发明提供了能够在利用现有技术的简单性的同时进行广播的通信系统，并且还提供并入通信系统的控制设备和信息处理系统。 在本发明中，芯片选择信号被提供用于独立地传输（TXCSi）和接收（RXCSi）以及如现有技术中的各个芯片。 也就是说，指示从节点是否被选择作为向主节点发送信号的节点和通信方向的一组信号从主节点输出到从节点。
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公开(公告)号：US07245248B2
公开(公告)日：2007-07-17
申请号：US10912542
申请日：2004-08-06
申请人： Yuichiro Morita , Kohei Sakurai , Nobuyasu Kanekawa , Masatoshi Hoshino , Hiromichi Yamada , Kotaro Shimamura , Satoshi Tanaka , Naoki Yada
发明人： Yuichiro Morita , Kohei Sakurai , Nobuyasu Kanekawa , Masatoshi Hoshino , Hiromichi Yamada , Kotaro Shimamura , Satoshi Tanaka , Naoki Yada
IPC分类号： H03M1/12
CPC分类号： H03M1/1225
摘要： In an A/D converter and a microcontroller including the same, the number of selection patterns of analog input channels is increased for each A/D conversion and the A/D conversion is conducted using an A/D converter having only fundamental functions without imposing load onto a CPU. The A/D converter or a DMA transfer device includes an A/D conversion table including one or more entries. Each entry includes enable bits for setting whether or not an A/D conversion is executed for the respective analog input channels and a plurality of count number bits for setting a number of executions of the A/D conversion.
摘要翻译： 在A / D转换器和包含该A / D转换器的微控制器中，对于每个A / D转换，模拟输入通道的选择模式的数量增加，并且使用仅具有基本功能的A / D转换器进行A / D转换，而不施加 加载到CPU上 A / D转换器或DMA传输装置包括包括一个或多个条目的A / D转换表。 每个条目包括用于设置是否对各个模拟输入通道执行A / D转换的使能位以及用于设置A / D转换执行次数的多个计数号位。
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17.发明申请Communications system, and informaton processing device and control device incorporating said communications system 失效通信系统，以及包含所述通信系统的信息处理装置和控制装置公开(公告)号：US20060036704A1
公开(公告)日：2006-02-16
申请号：US10980837
申请日：2004-11-04
申请人： Nobuyasu Kanekawa , Hiromichi Yamada , Kohei Sakurai , Kotaro Shimamura , Yuichiro Morita , Satoshi Tanaka
发明人： Nobuyasu Kanekawa , Hiromichi Yamada , Kohei Sakurai , Kotaro Shimamura , Yuichiro Morita , Satoshi Tanaka
IPC分类号： G06F15/16
CPC分类号： G06F13/4217
摘要： This invention provides communications systems that enable broadcasting while making use of the simplicity of the prior art and also provides control devices and information processing systems incorporating the communications system. In this invention, chip-select signals are provided for transmitting (TXCSi) and receiving (RXCSi) independently as well as for individual chips as in the prior art. That is, a group of signals indicating whether or not a slave node is selected as the node to transmit signals to a master node and the direction of communications are output from the master node to the slave node.
摘要翻译： 本发明提供了能够在利用现有技术的简单性的同时进行广播的通信系统，并且还提供并入通信系统的控制设备和信息处理系统。 在本发明中，芯片选择信号被提供用于独立地传输（TXCSi）和接收（RXCSi）以及如现有技术中的各个芯片。 也就是说，指示从节点是否被选择作为向主节点发送信号的节点和通信方向的一组信号从主节点输出到从节点。
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公开(公告)号：US20070124559A1
公开(公告)日：2007-05-31
申请号：US11604806
申请日：2006-11-28
IPC分类号： G06F12/00
CPC分类号： G06F11/167 , G06F11/08 , G06F11/183
摘要： A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.
摘要翻译： 提供了一种微控制器，其中硬件的增加被抑制，并且可以提高对RAM的软件错误的数据校正能力。 执行根据程序的处理的微控制器包括CPU和RAM，用于存储由CPU处理的数据，其中在RAM中定义复用区域，并且当这些区域被访问时，访问由CPU输出的地址和 执行通过向CPU输出的地址添加或减去某个值而获得的地址的复制访问。 通过这种方式，可以将相同的数据存储在多个区域中，并且可以提高可靠性。
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公开(公告)号：US07752527B2
公开(公告)日：2010-07-06
申请号：US11604806
申请日：2006-11-28
IPC分类号： G11C29/00
CPC分类号： G06F11/167 , G06F11/08 , G06F11/183
摘要： A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.
摘要翻译： 提供了一种微控制器，其中硬件的增加被抑制，并且可以提高对RAM的软件错误的数据校正能力。 执行根据程序的处理的微控制器包括CPU和RAM，用于存储由CPU处理的数据，其中在RAM中定义复用区域，并且当这些区域被访问时，访问由CPU输出的地址和 执行通过向CPU输出的地址添加或减去某个值而获得的地址的复制访问。 通过这种方式，可以将相同的数据存储在多个区域中，并且可以提高可靠性。
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公开(公告)号：US07260657B2
公开(公告)日：2007-08-21
申请号：US10491285
申请日：2001-10-02
摘要： A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer. A serial data transferring apparatus is realized which can simplify the structure of the slave unit, cut the total cost, and reduce noise.
摘要翻译： 主单元向从单元发送启动信号。 当从主单元接收到起始信号时，从单元向主单元发送同步字段，该同步字段是指示从单元能够执行传送和接收操作的传送时钟的数据串（脉冲信号） 。 主单元根据从从单元发送的同步字段指示的传送时钟向从属单元发送命令数据。 响应于从主单元发送的命令数据，从单元根据由同步字段指示的传送时钟向主单元发送响应数据。 因此，在采用本发明的串行数据传送装置的通信系统中，主单元建立用于数据传送的同步，而从单元没有建立用于数据传送的同步的负担。 实现了串行数据传送装置，其可以简化从单元的结构，降低总成本并降低噪声。
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