公开(公告)号：US08589612B2

公开(公告)日：2013-11-19

申请号：US13106788

申请日：2011-05-12

申请人： Hiromichi Yamada ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

发明人： Hiromichi Yamada ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F11/1641 ,  G06F2201/845

摘要： A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

摘要翻译： 提供一种缩短CPU的待机时间并提高从性能模式（并行操作）切换到安全模式（主/检测器操作）时的CPU处理效率的计算机系统。 在一个计算机系统中，包括：至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器，用于相互比较CPU的输出，分别由CPU执行相互不同的处理的性能模式之间进行切换，以提高CPU的性能和执行相同处理的安全模式，并将比较器的结果进行比较 检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。

公开(公告)号：US20050040978A1

公开(公告)日：2005-02-24

申请号：US10912542

申请日：2004-08-06

申请人： Yuichiro Morita ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Masatoshi Hoshino ,  Hiromichi Yamada ,  Kotaro Shimamura ,  Satoshi Tanaka ,  Naoki Yada

发明人： Yuichiro Morita ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Masatoshi Hoshino ,  Hiromichi Yamada ,  Kotaro Shimamura ,  Satoshi Tanaka ,  Naoki Yada

IPC分类号： H03M1/00 ,  H03M1/12

CPC分类号： H03M1/1225

摘要： In an A/D converter and a microcontroller including the same, the number of selection patterns of analog input channels is increased for each A/D conversion and the A/D conversion is conducted using an A/D converter having only fundamental functions without imposing load onto a CPU. The A/D converter or a DMA transfer device includes an A/D conversion table including one or more entries. Each entry includes enable bits for setting whether or not an A/D conversion is executed for the respective analog input channels and a plurality of count number bits for setting a number of executions of the A/D conversion.

摘要翻译： 在A / D转换器和包含该A / D转换器的微控制器中，对于每个A / D转换，模拟输入通道的选择模式的数量增加，并且使用仅具有基本功能的A / D转换器进行A / D转换，而不施加 加载到CPU上 A / D转换器或DMA传输装置包括包括一个或多个条目的A / D转换表。 每个条目包括用于设置是否对各个模拟输入通道执行A / D转换的使能位以及用于设置A / D转换执行次数的多个计数号位。

公开(公告)号：US20060036704A1

公开(公告)日：2006-02-16

申请号：US10980837

申请日：2004-11-04

申请人： Nobuyasu Kanekawa ,  Hiromichi Yamada ,  Kohei Sakurai ,  Kotaro Shimamura ,  Yuichiro Morita ,  Satoshi Tanaka

发明人： Nobuyasu Kanekawa ,  Hiromichi Yamada ,  Kohei Sakurai ,  Kotaro Shimamura ,  Yuichiro Morita ,  Satoshi Tanaka

IPC分类号： G06F15/16

CPC分类号： G06F13/4217

摘要： This invention provides communications systems that enable broadcasting while making use of the simplicity of the prior art and also provides control devices and information processing systems incorporating the communications system. In this invention, chip-select signals are provided for transmitting (TXCSi) and receiving (RXCSi) independently as well as for individual chips as in the prior art. That is, a group of signals indicating whether or not a slave node is selected as the node to transmit signals to a master node and the direction of communications are output from the master node to the slave node.

摘要翻译： 本发明提供了能够在利用现有技术的简单性的同时进行广播的通信系统，并且还提供并入通信系统的控制设备和信息处理系统。 在本发明中，芯片选择信号被提供用于独立地传输（TXCSi）和接收（RXCSi）以及如现有技术中的各个芯片。 也就是说，指示从节点是否被选择作为向主节点发送信号的节点和通信方向的一组信号从主节点输出到从节点。

公开(公告)号：US07765269B2

公开(公告)日：2010-07-27

申请号：US10980837

申请日：2004-11-04

申请人： Nobuyasu Kanekawa ,  Hiromichi Yamada ,  Kohei Sakurai ,  Kotaro Shimamura ,  Yuichiro Morita ,  Satoshi Tanaka

发明人： Nobuyasu Kanekawa ,  Hiromichi Yamada ,  Kohei Sakurai ,  Kotaro Shimamura ,  Yuichiro Morita ,  Satoshi Tanaka

IPC分类号： G06F15/16

CPC分类号： G06F13/4217

摘要： This invention provides communications systems that enable broadcasting while making use of the simplicity of the prior art and also provides control devices and information processing systems incorporating the communications system. In this invention, chip-select signals are provided for transmitting (TXCSi) and receiving (RXCSi) independently as well as for individual chips as in the prior art. That is, a group of signals indicating whether or not a slave node is selected as the node to transmit signals to a master node and the direction of communications are output from the master node to the slave node.

摘要翻译： 本发明提供了能够在利用现有技术的简单性的同时进行广播的通信系统，并且还提供并入通信系统的控制设备和信息处理系统。 在本发明中，芯片选择信号被提供用于独立地传输（TXCSi）和接收（RXCSi）以及如现有技术中的各个芯片。 也就是说，指示从节点是否被选择作为向主节点发送信号的节点和通信方向的一组信号从主节点输出到从节点。

公开(公告)号：US07245248B2

公开(公告)日：2007-07-17

申请号：US10912542

申请日：2004-08-06

申请人： Yuichiro Morita ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Masatoshi Hoshino ,  Hiromichi Yamada ,  Kotaro Shimamura ,  Satoshi Tanaka ,  Naoki Yada

发明人： Yuichiro Morita ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Masatoshi Hoshino ,  Hiromichi Yamada ,  Kotaro Shimamura ,  Satoshi Tanaka ,  Naoki Yada

IPC分类号： H03M1/12

CPC分类号： H03M1/1225

摘要： In an A/D converter and a microcontroller including the same, the number of selection patterns of analog input channels is increased for each A/D conversion and the A/D conversion is conducted using an A/D converter having only fundamental functions without imposing load onto a CPU. The A/D converter or a DMA transfer device includes an A/D conversion table including one or more entries. Each entry includes enable bits for setting whether or not an A/D conversion is executed for the respective analog input channels and a plurality of count number bits for setting a number of executions of the A/D conversion.

摘要翻译： 在A / D转换器和包含该A / D转换器的微控制器中，对于每个A / D转换，模拟输入通道的选择模式的数量增加，并且使用仅具有基本功能的A / D转换器进行A / D转换，而不施加 加载到CPU上 A / D转换器或DMA传输装置包括包括一个或多个条目的A / D转换表。 每个条目包括用于设置是否对各个模拟输入通道执行A / D转换的使能位以及用于设置A / D转换执行次数的多个计数号位。

公开(公告)号：US09323595B2

公开(公告)日：2016-04-26

申请号：US13555123

申请日：2012-07-21

申请人： Hiromichi Yamada ,  Teruaki Sakata ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro ,  Takashi Yasumasu ,  Kazuyoshi Fukuda ,  Kesami Hagiwara

发明人： Hiromichi Yamada ,  Teruaki Sakata ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro ,  Takashi Yasumasu ,  Kazuyoshi Fukuda ,  Kesami Hagiwara

IPC分类号： G05B19/29 ,  G06F11/07

CPC分类号： G06F11/0754 ,  G06F11/0739 ,  G06F13/00 ,  Y02D10/14

摘要： A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.

摘要翻译： 微控制器包括中央处理单元，根据由中央处理单元设置的PWM信号的生成条件产生PWM信号的PWM信号生成单元，以及在其中输入生成的PWM信号并检测脉冲周期的诊断单元 以及基于输入信号的脉冲宽度，并且确定检测到的脉冲周期和脉冲宽度是否与脉冲周期和对应于生成条件的脉冲宽度一致。

公开(公告)号：US20140032860A1

公开(公告)日：2014-01-30

申请号：US14110786

申请日：2011-04-21

申请人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata ,  Kesami Hagiwara ,  Yuichi Ishiguro

发明人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata ,  Kesami Hagiwara ,  Yuichi Ishiguro

IPC分类号： G06F12/02

CPC分类号： G06F12/02 ,  G06F11/1641 ,  G06F11/167 ,  G06F11/1687 ,  G06F2201/845

摘要： First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.

摘要翻译： 从功能模块（2）输出的要写入的第一数据被提供给内置存储器（3）和第一缓冲存储器（11），以及从功能模块（2）输出的要写入的第二数据 ）被提供给内置存储器（3）和第二缓冲存储器（12）。 第一和第二FIFO存储器（13,14）从从第一和第二缓冲存储器（11,12）顺次输出的多个第一和第二输出数据项中选择并存储具有预定数量的输出的数据项，以及 不要选择其他数据项。 比较器（15）将由第一和第二FIFO存储器（13,14）输出的具有预定数量的输出的数据项彼此进行比较。

公开(公告)号：US08639905B2

公开(公告)日：2014-01-28

申请号：US13614313

申请日：2012-09-13

申请人： Hiromichi Yamada ,  Yuichi Ishiguro ,  Nobuyasu Kanekawa

发明人： Hiromichi Yamada ,  Yuichi Ishiguro ,  Nobuyasu Kanekawa

IPC分类号： G06F12/02

CPC分类号： G06F11/1641 ,  G06F11/1683

摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

摘要翻译： 其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。 微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入 两次，并且第一次和第二次的写入数据被相互整理。

公开(公告)号：US09367438B2

公开(公告)日：2016-06-14

申请号：US14110786

申请日：2011-04-21

申请人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata ,  Kesami Hagiwara ,  Yuichi Ishiguro

发明人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata ,  Kesami Hagiwara ,  Yuichi Ishiguro

IPC分类号： G06F12/02 ,  G06F11/16

CPC分类号： G06F12/02 ,  G06F11/1641 ,  G06F11/167 ,  G06F11/1687 ,  G06F2201/845

摘要： First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.

摘要翻译： 从功能模块（2）输出的要写入的第一数据被提供给内置存储器（3）和第一缓冲存储器（11），以及从功能模块（2）输出的要写入的第二数据 ）被提供给内置存储器（3）和第二缓冲存储器（12）。 第一和第二FIFO存储器（13,14）从从第一和第二缓冲存储器（11,12）顺次输出的多个第一和第二输出数据项中选择并存储具有预定数量的输出的数据项，以及 不要选择其他数据项。 比较器（15）将由第一和第二FIFO存储器（13,14）输出的具有预定数量的输出的数据项彼此进行比较。

公开(公告)号：US08291188B2

公开(公告)日：2012-10-16

申请号：US12706938

申请日：2010-02-17

申请人： Hiromichi Yamada ,  Yuichi Ishiguro ,  Nobuyasu Kanekawa

发明人： Hiromichi Yamada ,  Yuichi Ishiguro ,  Nobuyasu Kanekawa

IPC分类号： G06F12/12

CPC分类号： G06F11/1641 ,  G06F11/1683

摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

摘要翻译： 其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。 微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入 两次，并且第一次和第二次的写入数据被相互整理。