公开(公告)号：US5977820A

公开(公告)日：1999-11-02

申请号：US47416

申请日：1998-03-25

申请人： Yasushi Sogabe ,  Fumio Ishizu ,  Keishi Murakami

发明人： Yasushi Sogabe ,  Fumio Ishizu ,  Keishi Murakami

IPC分类号： H04L27/22 ,  H04L7/00 ,  H04L7/027 ,  H03D3/00 ,  H04L27/38

CPC分类号： H04L7/027

摘要： The presence or absence of a clock component is detected for an input signal. If the input signal does not comprise a clock component, the operation of a computing circuit is halted, thereby further improving the accuracy of phase estimation. A signal generating circuit produces a twiddle factor for DFT. A DFT circuit performs discrete Fourier transform on an input signal for a predetermined number of symbols based on the twiddle factor for DFT. A pattern detecting circuit examines the input signal for its pattern based on the output from the DFT circuit. An averaging filter turns on or off the operation of the subsequent averaging filter according to the detected pattern, and averages the outputs from the DFT circuit to remove a noise component.

摘要翻译： 检测到输入信号是否存在时钟分量。 如果输入信号不包括时钟分量，则停止计算电路的操作，从而进一步提高相位估计的精度。 信号发生电路为DFT产生旋转因子。 DFT电路基于用于DFT的旋转因子对预定数量的符号对输入信号执行离散傅里叶变换。 模式检测电路根据DFT电路的输出检查其模式的输入信号。 平均滤波器根据检测到的模式打开或关闭随后的平均滤波器的操作，并平均来自DFT电路的输出以去除噪声分量。

公开(公告)号：US06731910B2

公开(公告)日：2004-05-04

申请号：US09097677

申请日：1998-06-16

申请人： Akinori Taira ,  Fumio Ishizu ,  Keishi Murakami

发明人： Akinori Taira ,  Fumio Ishizu ,  Keishi Murakami

IPC分类号： H04B100

CPC分类号： H04B7/0811 ,  H03G3/3036 ,  H04B1/1081 ,  H04B7/0608 ,  H04B7/0814 ,  H04B17/318 ,  H04L7/04 ,  H04W52/32 ,  H04W52/40 ,  H04W52/52 ,  H04W52/54

摘要： In a data transmission system, a transmitter adds control data to transmission data, and modulates the resultant signal by a predetermined modulation method, and sends the result in a wireless manner. A receiver detects a reception power intensity by use of the control data contained in the transmitted signal. A random pattern is used for a reception-power detecting portion for detecting a reception power intensity, which is contained in the control data.

公开(公告)号：US06347126B1

公开(公告)日：2002-02-12

申请号：US09185744

申请日：1998-11-04

申请人： Takayuki Nagayasu ,  Keishi Murakami

发明人： Takayuki Nagayasu ,  Keishi Murakami

IPC分类号： H04L2706

CPC分类号： H04L25/0236 ,  H03J7/02 ,  H04B7/01 ,  H04L25/0212 ,  H04L25/0226 ,  H04L25/025 ,  H04L25/03273 ,  H04L25/03292 ,  H04L27/0014 ,  H04L2027/0038 ,  H04L2027/0055 ,  H04L2027/0059 ,  H04L2027/0067

摘要： Distortion of a received signal due to intersymbol interference as well as to frequency offset is corrected. For this reason, a frequency offset correcting circuit 21 corrects a received signal based on a frequency-offset estimated value. A first CIR estimating circuit 22 estimates CIR estimated values at a first position according to a known training sequence in the corrected received signal. Also, a second estimating circuit 24 updates the CIR estimated values with the LMS algorithm according to the corrected received signals as well as to the decision value outputted from the equalizer 13 with the CIR estimated values at the first position as initial values and obtains CIR estimated values at a second position apart from the first position. A phase deviation detecting circuit 15 computes phase deviations based on CIR estimated values at the first position as well as on CIR estimated values at the second position, and an averaging circuit 26 averages the phase deviations, and outputs the averaged value to the frequency offset correcting circuit 21 as a frequency-offset estimated value.

摘要翻译： 校正了由于符号间干扰以及频率偏移引起的接收信号的失真。 为此，频偏校正电路21基于频偏估计值来校正接收信号。 第一CIR估计电路22根据校正的接收信号中的已知训练序列来估计第一位置处的CIR估计值。 此外，第二估计电路24根据校正后的接收信号，利用LMS算法对CIR估计值进行更新，以及以第一位置的CIR估计值作为初始值从均衡器13输出的判定值，并获得CIR估计值 在距离第一位置的第二位置处的值。 相位偏差检测电路15基于第一位置处的CIR估计值以及第二位置处的CIR估计值来计算相位偏差，并且平均电路26对相位偏差进行平均，并将平均值输出到频率偏移校正 电路21作为频偏估计值。

公开(公告)号：US06269124B1

公开(公告)日：2001-07-31

申请号：US09087926

申请日：1998-06-01

申请人： Takayuki Nagayasu ,  Keishi Murakami

发明人： Takayuki Nagayasu ,  Keishi Murakami

IPC分类号： H04L2302

CPC分类号： H04L1/0051 ,  H03M13/3776 ,  H03M13/41 ,  H03M13/4146 ,  H03M13/45 ,  H04L1/0054 ,  H04L25/0202

摘要： A data transmission system, a receiver, and a recording medium in which a re-coder (16) generates pseudo transmission signals based on the virtual received data after a decoder (15) generates virtual received data based on virtual decision data from a virtual decision circuit (12), and a soft-decision circuit (18) outputs soft-decision data so as to decrease the number of different bits between the pseudo transmission signals and the received signals, and the received data are generated based on the soft-decision data.

摘要翻译： 一种数据传输系统，接收机和记录介质，其中重新编码器（16）基于虚拟接收数据在解码器（15）基于来自虚拟决策的虚拟决策数据生成虚拟接收数据之后生成伪传输信号 电路（12）和软判决电路（18）输出软判决数据，以便减少伪发送信号与接收信号之间的不同比特数，并且基于软判决生成接收的数据 数据。

公开(公告)号：US5475710A

公开(公告)日：1995-12-12

申请号：US998517

申请日：1992-12-29

申请人： Fumio Ishizu ,  Kouji Ueda ,  Keishi Murakami

发明人： Fumio Ishizu ,  Kouji Ueda ,  Keishi Murakami

IPC分类号： H03H21/00 ,  H03H15/00 ,  H03H17/00 ,  H03H17/02 ,  H04B3/14 ,  H04L7/08 ,  H04L25/03 ,  H04L27/00 ,  H04L27/233 ,  H03H7/30 ,  H03H7/40 ,  H04L7/00 ,  H04L27/06

CPC分类号： H04L27/2332 ,  H04L25/03057 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0095

摘要： A receiver capable of effecting frame synchronization control even at the time of initial acquisition and hand off in the presence of frequency selective fading. The receiver is provided in a demodulator part thereof with a quasi-coherent detector (140), a memory (144) for temporarily storing the output of the quasi-coherent detector, a write address counter (145) for the memory, an incoherent correlator (146) that determines correlation between a received data pattern and a known UW data pattern, a UW tentative detection circuit (147) that is supplied with the output of the address counter and the output of the incoherent correlator, an adaptive equalizer (148) that equalizes the received data stored in the memory by using the output of the UW tentative detection circuit, a UW detector (103) that effects UW position detection on the basis of the equalized data, and a frame synchronization control circuit (150) that effects frame synchronization control on the basis of the output of the UW tentative detection circuit and the output of the UW detector.

摘要翻译： 即使在频率选择性衰落存在的情况下，即使在初始采集时也能执行帧同步控制的接收机。 接收机在其解调器部分中提供准相干检测器（140），用于临时存储准相干检测器的输出的存储器（144），用于存储器的写地址计数器（145），非相干相关器 （146），其确定接收的数据模式与已知UW数据模式之间的相关性;被提供有地址计数器的输出和非相干相关器的输出的UW临时检测电路（147），自适应均衡器（148） 通过使用UW临时检测电路的输出，通过基于均衡数据实现UW位置检测的UW检测器（103）来均衡存储在存储器中的接收数据;以及帧同步控制电路（150），其实现 基于UW临时检测电路的输出和UW检测器的输出进行帧同步控制。