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    Sequence estimation method and sequence estimator
    2.
    发明授权
    Sequence estimation method and sequence estimator 失效

    公开(公告)号：US06996196B2

    公开(公告)日：2006-02-07

    申请号：US10315131

    申请日：2002-12-10

    申请人： Hiroshi Kubo ,  Kazuo Tanada ,  Keishi Murakami

    发明人： Hiroshi Kubo ,  Kazuo Tanada ,  Keishi Murakami

    IPC分类号： H04L27/06 ,  H03M13/03

    CPC分类号： H04L25/03191

    摘要： In a sequence estimation method and a sequence estimator of the present invention, a metric is calculated using a received signal and its estimated value, also another metric is calculated using a filtering result via a matching filter, one of these metrics is selected based on a characteristic of the channel or these metrics are combined, when a transmitted signal sequence transmitted from a transmission side is estimated based on a characteristic of a received signal and a channel using a list output Viterbi algorithm for deciding one or a plurality of survivors for each state of the Viterbi algorithm including one or more states. The operation speed and the characteristic of a channel can be improved using the smallest circuit scale even if the characteristic of a channel has a long delay time, in a sequence estimation method and a sequence estimator.

    Equalizer
    3.
    发明授权
    Equalizer 失效
    均衡器

    公开(公告)号：US5068873A

    公开(公告)日：1991-11-26

    申请号：US604940

    申请日：1990-10-29

    申请人： Keishi Murakami

    发明人： Keishi Murakami

    IPC分类号： H04L25/03

    CPC分类号： H04L25/03057

    摘要： "An adaptive equalizer comprising a computer unit which receives a known signals sequence to estimate transmission channel characteristics and effect compensatory control of tap coefficients by use of a first algorithm that has fast convergence property, and a tap coefficient computing unit for making compensation for relatively slow changes in a random data input after the compensation for the transmission channel characteristics, which either employs an algorithm that involves a relatively low computational complexity or intermittently executes computation."

    Method of sequence estimation
    4.
    发明授权
    Method of sequence estimation 有权
    序列估计方法

    公开(公告)号：US06314387B1

    公开(公告)日：2001-11-06

    申请号：US09171531

    申请日：1998-11-30

    申请人： Hiroshi Kubo ,  Keishi Murakami

    发明人： Hiroshi Kubo ,  Keishi Murakami

    IPC分类号： H01L2706

    CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H04L1/0054 ,  H04L1/006

    摘要： The prior art method of estimating a sequence by making use of a Viterbi algorithm is modified as follows: (1) A path at a certain past instant is modified to derive a modified path. (2) The path metric value of the modified path is calculated. (3) The path metric of a normal path and the path metric of the modified path are compared. If the path metric of the modified path is smaller, the path is modified. (4) A surviving path is selected from plural paths passing through the modified path.

    摘要翻译： 通过使用维特比算法估计序列的现有技术方法如下修改：（1）修改某一过去时刻的路径以导出修改的路径。 （2）计算修改路径的路径度量值。 （3）比较正常路径的路径度量和修改路径的路径度量。 如果修改路径的路径度量较小，则修改路径。 （4）从通过修改路径的多个路径中选择存活路径。

    Digital data demodulating device for estimating channel impulse response
    5.
    发明授权
    Digital data demodulating device for estimating channel impulse response 失效
    用于估计信道脉冲响应的数字数据解调装置

    公开(公告)号：US06219388B1

    公开(公告)日：2001-04-17

    申请号：US09007533

    申请日：1998-01-15

    申请人： Kazuo Tanada ,  Hiroshi Kubo ,  Keishi Murakami

    发明人： Kazuo Tanada ,  Hiroshi Kubo ,  Keishi Murakami

    IPC分类号： H03D100

    CPC分类号： H04L25/0212 ,  H04L25/03292

    摘要： A digital data demodulating device that estimates the channel impulse response (CIR) based on a received signal, and performs a viterbi algorithm using the replica generated according to the estimated CIR, and the received signal. The digital data demodulating device of the present invention follows the time variation of the channel by sequentially estimating the CIR in the CIR estimating circuit. The replica generating circuit of the digital data demodulating device includes a device for storing the estimated CIR and replica for each block therein, for reading the estimated CIR at a specific timing and updating the replica. A digital data demodulating device which reduce circuit scale, operates in a high speed, and appropriately follows the time variation of the channel, even in a high bit transmission rate and in a high delay dispersion of the multipass wave contained in the received signal.

    摘要翻译： 一种数字数据解调装置，其基于接收信号估计信道脉冲响应（CIR），并使用根据所估计的CIR产生的副本和所接收的信号执行维特比算法。 本发明的数字数据解调装置通过顺序估计CIR估计电路中的CIR，跟随信道的时间变化。 数字数据解调装置的复制品生成电路包括用于存储估计的CIR和用于每个块的副本的装置，用于在特定定时读取估计的CIR并更新副本。 即使在包含在接收信号中的多通道波的高位传输速率和高延迟色散中，数字数据解调装置降低电路规模，高速运行，并适当地跟随信道的时间变化。

    Phase estimating circuit and demodulating circuit
    6.
    发明授权
    Phase estimating circuit and demodulating circuit 失效
    相位估计电路和解调电路

    公开(公告)号：US5977820A

    公开(公告)日：1999-11-02

    申请号：US47416

    申请日：1998-03-25

    申请人： Yasushi Sogabe ,  Fumio Ishizu ,  Keishi Murakami

    发明人： Yasushi Sogabe ,  Fumio Ishizu ,  Keishi Murakami

    IPC分类号： H04L27/22 ,  H04L7/00 ,  H04L7/027 ,  H03D3/00 ,  H04L27/38

    CPC分类号： H04L7/027

    摘要： The presence or absence of a clock component is detected for an input signal. If the input signal does not comprise a clock component, the operation of a computing circuit is halted, thereby further improving the accuracy of phase estimation. A signal generating circuit produces a twiddle factor for DFT. A DFT circuit performs discrete Fourier transform on an input signal for a predetermined number of symbols based on the twiddle factor for DFT. A pattern detecting circuit examines the input signal for its pattern based on the output from the DFT circuit. An averaging filter turns on or off the operation of the subsequent averaging filter according to the detected pattern, and averages the outputs from the DFT circuit to remove a noise component.

    摘要翻译： 检测到输入信号是否存在时钟分量。 如果输入信号不包括时钟分量，则停止计算电路的操作，从而进一步提高相位估计的精度。 信号发生电路为DFT产生旋转因子。 DFT电路基于用于DFT的旋转因子对预定数量的符号对输入信号执行离散傅里叶变换。 模式检测电路根据DFT电路的输出检查其模式的输入信号。 平均滤波器根据检测到的模式打开或关闭随后的平均滤波器的操作，并平均来自DFT电路的输出以去除噪声分量。

    Sequence estimation method and sequence estimator
    8.
    发明授权
    Sequence estimation method and sequence estimator 失效
    序列估计方法和序列估计器

    公开(公告)号：US06556632B1

    公开(公告)日：2003-04-29

    申请号：US09083507

    申请日：1998-05-22

    申请人： Hiroshi Kubo ,  Kazuo Tanada ,  Keishi Murakami

    发明人： Hiroshi Kubo ,  Kazuo Tanada ,  Keishi Murakami

    IPC分类号： H04L2706

    CPC分类号： H04L25/03191

    摘要： In a sequence estimation method and a sequence estimator of the present invention, a metric is calculated using a received signal and its estimated value, also another metric is calculated using a filtering result via a matching filter, one of these metrics is selected based on a characteristic of the channel or these metrics are combined, when a transmitted signal sequence transmitted from a transmission side is estimated based on a characteristic of a received signal and a channel using a list output Viterbi algorithm for deciding one or a plurality of survivors for each state of the Viterbi algorithm including one or more states. The operation speed and the characteristic of a channel can be improved using the smallest circuit scale even if the characteristic of a channel has a long delay time, in a sequence estimation method and a sequence estimator.

    摘要翻译： 在本发明的序列估计方法和序列估计器中，使用接收信号及其估计值来计算度量，并且使用经过匹配滤波器的滤波结果来计算另一度量，这些度量之一是基于 当从发送侧发送的发送信号序列基于接收信号的特性和使用列表输出维特比算法的信道来估计每个状态的一个或多个幸存者时，将信道或这些度量的特征组合 维特比算法包括一个或多个状态。 在序列估计方法和序列估计器中，即使信道的特性具有较长的延迟时间，也可以使用最小的电路规模来提高信道的操作速度和特性。

    Receiver with a frequency offset correcting function
    9.
    发明授权
    Receiver with a frequency offset correcting function 失效
    具有频偏补偿功能的接收机

    公开(公告)号：US06347126B1

    公开(公告)日：2002-02-12

    申请号：US09185744

    申请日：1998-11-04

    申请人： Takayuki Nagayasu ,  Keishi Murakami

    发明人： Takayuki Nagayasu ,  Keishi Murakami

    IPC分类号： H04L2706

    CPC分类号： H04L25/0236 ,  H03J7/02 ,  H04B7/01 ,  H04L25/0212 ,  H04L25/0226 ,  H04L25/025 ,  H04L25/03273 ,  H04L25/03292 ,  H04L27/0014 ,  H04L2027/0038 ,  H04L2027/0055 ,  H04L2027/0059 ,  H04L2027/0067

    摘要： Distortion of a received signal due to intersymbol interference as well as to frequency offset is corrected. For this reason, a frequency offset correcting circuit 21 corrects a received signal based on a frequency-offset estimated value. A first CIR estimating circuit 22 estimates CIR estimated values at a first position according to a known training sequence in the corrected received signal. Also, a second estimating circuit 24 updates the CIR estimated values with the LMS algorithm according to the corrected received signals as well as to the decision value outputted from the equalizer 13 with the CIR estimated values at the first position as initial values and obtains CIR estimated values at a second position apart from the first position. A phase deviation detecting circuit 15 computes phase deviations based on CIR estimated values at the first position as well as on CIR estimated values at the second position, and an averaging circuit 26 averages the phase deviations, and outputs the averaged value to the frequency offset correcting circuit 21 as a frequency-offset estimated value.

    摘要翻译： 校正了由于符号间干扰以及频率偏移引起的接收信号的失真。 为此，频偏校正电路21基于频偏估计值来校正接收信号。 第一CIR估计电路22根据校正的接收信号中的已知训练序列来估计第一位置处的CIR估计值。 此外，第二估计电路24根据校正后的接收信号，利用LMS算法对CIR估计值进行更新，以及以第一位置的CIR估计值作为初始值从均衡器13输出的判定值，并获得CIR估计值 在距离第一位置的第二位置处的值。 相位偏差检测电路15基于第一位置处的CIR估计值以及第二位置处的CIR估计值来计算相位偏差，并且平均电路26对相位偏差进行平均，并将平均值输出到频率偏移校正 电路21作为频偏估计值。

    Data transmission system, receiver, and recording medium
    10.
    发明授权
    Data transmission system, receiver, and recording medium 失效
    数据传输系统，接收机和记录介质

    公开(公告)号：US06269124B1

    公开(公告)日：2001-07-31

    申请号：US09087926

    申请日：1998-06-01

    申请人： Takayuki Nagayasu ,  Keishi Murakami

    发明人： Takayuki Nagayasu ,  Keishi Murakami

    IPC分类号： H04L2302

    CPC分类号： H04L1/0051 ,  H03M13/3776 ,  H03M13/41 ,  H03M13/4146 ,  H03M13/45 ,  H04L1/0054 ,  H04L25/0202

    摘要： A data transmission system, a receiver, and a recording medium in which a re-coder (16) generates pseudo transmission signals based on the virtual received data after a decoder (15) generates virtual received data based on virtual decision data from a virtual decision circuit (12), and a soft-decision circuit (18) outputs soft-decision data so as to decrease the number of different bits between the pseudo transmission signals and the received signals, and the received data are generated based on the soft-decision data.

    摘要翻译： 一种数据传输系统，接收机和记录介质，其中重新编码器（16）基于虚拟接收数据在解码器（15）基于来自虚拟决策的虚拟决策数据生成虚拟接收数据之后生成伪传输信号 电路（12）和软判决电路（18）输出软判决数据，以便减少伪发送信号与接收信号之间的不同比特数，并且基于软判决生成接收的数据 数据。