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    Packet switching system having self-routing switches
    12.
    发明授权
    Packet switching system having self-routing switches 失效
    分组交换系统具有自路由交换机

    公开(公告)号：US5740156A

    公开(公告)日：1998-04-14

    申请号：US645491

    申请日：1991-01-24

    申请人： Shirou Tanabe ,  Taihei Suzuki ,  Shinobu Gohara ,  Yoshito Sakurai ,  Kenichi Ohtsuki ,  Takao Kato ,  Hiroshi Kuwahara ,  Eiichi Amada

    发明人： Shirou Tanabe ,  Taihei Suzuki ,  Shinobu Gohara ,  Yoshito Sakurai ,  Kenichi Ohtsuki ,  Takao Kato ,  Hiroshi Kuwahara ,  Eiichi Amada

    IPC分类号： H04L12/56 ,  H04L12/64 ,  H04Q11/04

    CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04Q11/0421 ,  H04L2012/5652 ,  H04L2012/6481

    摘要： A packet switching system which includes a device for setting, between a tandem unit and a destination local unit, the same logic channel as that between an originating local unit operative for information transfer and the tandem unit in respect of a call destined for a local unit other than the originating local unit and a device, operable in the originating-side local unit for information transfer, for inserting output port information of a self-routing switch inside the tandem unit into a packet destined for the local unit other than this local unit. In the tandem unit, setting of logic channel conversion information is not required to be done and even when any control signal packet from the originating local unit arrives at the tandem unit, the packet is transferred to the destination local unit without undergoing termination of packet and concomitant call processing control.

    摘要翻译： 分组交换系统，其包括用于在串联单元和目的地本地单元之间设置与用于信息传输的起始本地单元和针对本地单元的呼叫相关的串联单元之间的相同逻辑信道的设备 除了起始本地单元和可在始发方本地单元中进行信息传输的装置，用于将串联单元内的自路由交换机的输出端口信息插入到本地单元以外的本地单元的分组中 。 在串联单元中，逻辑信道转换信息的设置不需要完成，即使来自始发本地单元的任何控制信号分组到达串行单元，分组被传送到目的地本地单元，而不会发生分组的终止， 伴随呼叫处理控制。

    ATM cell switching system
    15.
    发明授权
    ATM cell switching system 失效
    ATM信元交换系统

    公开(公告)号：US06728242B2

    公开(公告)日：2004-04-27

    申请号：US10374998

    申请日：2003-02-28

    申请人： Yoshito Sakurai ,  Kenichi Ohtsuki ,  Shinobu Gohara ,  Makoto Mori ,  Akira Horiki ,  Takao Kato ,  Hiroshi Kuwahara

    发明人： Yoshito Sakurai ,  Kenichi Ohtsuki ,  Shinobu Gohara ,  Makoto Mori ,  Akira Horiki ,  Takao Kato ,  Hiroshi Kuwahara

    IPC分类号： H04L1256

    CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682 ,  H04Q11/0478

    摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

    摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。