公开(公告)号：US07076754B2

公开(公告)日：2006-07-11

申请号：US10635499

申请日：2003-08-07

申请人： Tetsuo Miyamoto

发明人： Tetsuo Miyamoto

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： A functional block design method capable of shortening the period needed for developing functional blocks in compliance with orders. A logic design is prepared for a desired number of memory floor plan blocks with respective predetermined data storage capacities and a fixed block different from the memory floor plan blocks, and block-based design data is created in compliance with the logic design. The created block-based design data is verified in that a constraint on the creation of a CPU macro is always fulfilled within the limits up to which the memory blocks can be mounted. Using the verified block-based design data, design data of a CPU macro functional block in which a desired number of memory blocks corresponding to a desired memory capacity are connected to the fixed block is generated.

摘要翻译： 一种功能块设计方法，能够缩短按顺序开发功能块所需的时间。 为具有各自的预定数据存储容量的期望数量的存储器平面图块和与存储器平面图块不同的固定块准备逻辑设计，并且根据逻辑设计创建基于块的设计数据。 验证了创建的基于块的设计数据，因为在可以安装存储器块的范围内始终满足对创建CPU宏的约束。 使用经验证的基于块的设计数据，生成其中与期望的存储器容量相对应的期望数量的存储器块连接到固定块的CPU宏功能块的设计数据。

公开(公告)号：US5729387A

公开(公告)日：1998-03-17

申请号：US831182

申请日：1997-04-02

申请人： Kazuo Takahashi ,  Norioki Fujimoto ,  Masashi Takazawa ,  Takashi Odaira ,  Tomohito Koizumi ,  Kiyondo Kobayashi ,  Syozo Kato ,  Tetsuo Miyamoto ,  Mamoru Kubo

发明人： Kazuo Takahashi ,  Norioki Fujimoto ,  Masashi Takazawa ,  Takashi Odaira ,  Tomohito Koizumi ,  Kiyondo Kobayashi ,  Syozo Kato ,  Tetsuo Miyamoto ,  Mamoru Kubo

IPC分类号： F21S11/00 ,  F21V5/02 ,  F21V17/02 ,  F24J2/06 ,  F24J2/40 ,  F04B7/18 ,  G02B17/00

CPC分类号： F24J2/062 ,  F21S11/00 ,  F24J2/06 ,  F24J2/40 ,  Y02E10/44

摘要： A solar lighting apparatus according to the present inveniton is configured so that one lighting prism plate is rotatably arranged in a lighting portion or a plurality of lighting prism plates are rotatably arranged in the lighting portion at intervals of a predetermined distance, and a prism angle of each the lighting prism plate is controlled correspondingly to the height and azimuth of the sun so that the sunlight refracted by the lighting prism plates goes out in a predetermined direction. Therefor, the lighting prism plates and parts relevant thereto are formed under predetermined conditions. A solar lighting controller in a solar lighting apparatus operated under predetermined conditions for improvement of lighting efficiency, reduction of consumed electric power, etc., the controller comprising a solar position detector, a central processing unit including an arithmetic operation storage means such as a micro computer and a necessary means such as an optical axis sensor.

摘要翻译： 根据本发明的太阳能照明装置被配置为使得一个采光棱镜板可旋转地布置在照明部分中，或者多个采光棱镜板以预定距离的间隔可旋转地布置在照明部分中，并且棱镜角 每个采光棱镜板对应于太阳的高度和方位来控制，使得由采光棱镜板折射的阳光在预定方向上熄灭。 因此，在预定条件下形成采光棱镜板及与其相关的部件。 一种在预定条件下操作以提高照明效率，降低消耗电力等的太阳能照明装置中的太阳能照明控制器，所述控制器包括太阳能位置检测器，中央处理单元，其包括算术运算存储装置，例如微型 计算机和必要的手段，例如光轴传感器。

公开(公告)号：US5603861A

公开(公告)日：1997-02-18

申请号：US424522

申请日：1995-05-26

申请人： Nobuharu Umamori ,  Tetsuo Miyamoto ,  Makoto Kanbara ,  Hirotaka Tomizawa

发明人： Nobuharu Umamori ,  Tetsuo Miyamoto ,  Makoto Kanbara ,  Hirotaka Tomizawa

IPC分类号： C10M171/00 ,  C10M169/04

CPC分类号： C10M171/001

摘要： An electroviscous fluid wherein an electrically insulating fluid is mixed with silica fine particles having esterified surfaces, and a polyhydric alcohol. Thus, it is possible to provide an electroviscous fluid which is excellent in dispersion stability and shelf stability, free from aggregation of particles even under heating conditions and capable of manifesting high electroviscous effect.

摘要翻译： PCT No.PCT / JP94 / 01592 Sec。 371日期：1995年5月26日 102（e）日期1995年5月26日PCT 1994年9月28日PCT公布。 第WO95 / 09221号公报 日期1995年4月6日电气流体，其中电绝缘流体与具有酯化表面的二氧化硅细颗粒和多元醇混合。 因此，可以提供分散稳定性和贮存稳定性优异的电粘性流体，即使在加热条件下也不会产生颗粒聚集，并且能够表现出高的电粘效果。

公开(公告)号：US07729200B2

公开(公告)日：2010-06-01

申请号：US12000840

申请日：2007-12-18

申请人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/10

CPC分类号： G11C8/12 ,  G06F12/0207

摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

公开(公告)号：US07650451B2

公开(公告)日：2010-01-19

申请号：US11790337

申请日：2007-04-25

申请人： Tetsuo Miyamoto ,  Yasuhiro Watanabe

发明人： Tetsuo Miyamoto ,  Yasuhiro Watanabe

IPC分类号： G06F13/362

CPC分类号： G06F13/364

摘要： An arbiter circuit includes a priority coefficient calculating unit, a priority coefficient comparator an acceptance determining unit, and a priority determining unit. The priority coefficient calculating unit calculates for each request an arbitration priority coefficient based on a priority level set for each request by requesters. The priority coefficient comparator compares arbitration priority coefficients calculated for the requesters by the priority coefficient calculating unit. The acceptance determining unit determines whether to accept the requests based on the comparison result by the priority coefficient comparator. When the arbitration priority coefficient calculated by the priority coefficient calculating unit is equal between two or more requests, the priority determining unit determines a priority order for accepting the requests.

摘要翻译： 仲裁器电路包括优先级系数计算单元，优先级系数比较器，接受确定单元和优先级确定单元。 优先级系数计算单元基于为请求者针对每个请求设置的优先级来为每个请求计算仲裁优先级系数。 优先级系数比较器比较由优先级系数计算单元计算的请求者的仲裁优先级系数。 接受确定单元基于优先级系数比较器的比较结果确定是否接受请求。 当由优先级系数计算单元计算的仲裁优先级系数在两个或更多个请求之间相等时，优先级确定单元确定接受请求的优先顺序。

公开(公告)号：US20090027988A1

公开(公告)日：2009-01-29

申请号：US12000953

申请日：2007-12-19

申请人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4087 ,  G09G5/393 ,  G09G5/395 ,  G11C8/12

摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储器单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

公开(公告)号：US20080189467A1

公开(公告)日：2008-08-07

申请号：US12000840

申请日：2007-12-18

申请人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G06F12/00

CPC分类号： G11C8/12 ,  G06F12/0207

摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

公开(公告)号：US20080151670A1

公开(公告)日：2008-06-26

申请号：US11709867

申请日：2007-02-23

申请人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

摘要翻译： 提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控​​制器及其存储器系统。 响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作， 并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作 在刷新目标银行。

公开(公告)号：US06799310B2

公开(公告)日：2004-09-28

申请号：US10325964

申请日：2002-12-23

申请人： Tetsuo Miyamoto

发明人： Tetsuo Miyamoto

IPC分类号： G06F1750

CPC分类号： G06F17/5072

摘要： An integrated circuit layout method for placing a plurality of cells within a chip comprises a process for sorting the plurality of cells (or function macros) that are to be laid out in order of their delay times (or operation speed margins for macro), placing cells (or macros) having the largest delay times (or smallest speed margin for macro) closer to the peripheral area of the chip, and as the cell delay times get smaller(or the speed margins get larger), placing the relevant cells (or macros) closer to the central area of the chip.

摘要翻译： 用于将多个单元放置在芯片内的集成电路布局方法包括按照它们的延迟时间（或宏的操作速度裕度）的顺序排列要布置的多个单元（或功能宏）的处理， 更靠近芯片的周边区域的延迟时间（或宏的最小速度裕度）的单元（或宏），并且随着单元延迟时间变小（或速度裕度变大），放置相关单元（或 宏）更靠近芯片的中心区域。

公开(公告)号：US5387370A

公开(公告)日：1995-02-07

申请号：US30022

申请日：1993-03-24

申请人： Hirotaka Tomizawa ,  Makoto Kanbara ,  Tetsuo Miyamoto

发明人： Hirotaka Tomizawa ,  Makoto Kanbara ,  Tetsuo Miyamoto

IPC分类号： C10M171/00 ,  C09K19/52 ,  C09K5/00 ,  H01B3/24

CPC分类号： C10M171/001 ,  C09K19/0225 ,  C09K19/2021 ,  C09K2019/2035 ,  C09K2019/521

摘要： Electroviscous fluid according to the present invention is used for vibration control machines and devices such as variable damper, engine mount, bearing damper, clutch, valve, shock absorber, precision machine, accoustic machine, etc. and for display element. It has high electroviscous effect and wider application temperature range, and the electroviscous effect is stable.

摘要翻译： PCT No.PCT / JP92 / 00944 Sec。 371日期1993年3月24日 102（e）日期1993年3月24日PCT提交1992年7月24日PCT公布。 出版物WO93 / 02166 日本：1993年2月4日。根据本发明的电磁流体用于诸如可变阻尼器，发动机支架，轴承阻尼器，离合器，阀，减震器，精密机械，声学机械等的振动控制机器和装置 显示元素。 电解效果好，使用温度范围广，电粘效果稳定。