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28 条记录 (耗时 0.031 秒)

    Arbiter circuit
    1.
    发明申请
    Arbiter circuit 有权
    仲裁电路

    公开(公告)号：US20080046611A1

    公开(公告)日：2008-02-21

    申请号：US11790337

    申请日：2007-04-25

    申请人： Tetsuo Miyamoto ,  Yasuhiro Watanabe

    发明人： Tetsuo Miyamoto ,  Yasuhiro Watanabe

    IPC分类号： G06F3/00

    CPC分类号： G06F13/364

    摘要： An arbiter circuit includes a priority coefficient calculating unit, a priority coefficient comparator an acceptance determining unit, and a priority determining unit. The priority coefficient calculating unit calculates for each request an arbitration priority coefficient based on a priority level set for each request by requesters. The priority coefficient comparator compares arbitration priority coefficients calculated for the requesters by the priority coefficient calculating unit. The acceptance determining unit determines whether to accept the requests based on the comparison result by the priority coefficient comparator. When the arbitration priority coefficient calculated by the priority coefficient calculating unit is equal between two or more requests, the priority determining unit determines a priority order for accepting the requests.

    摘要翻译： 仲裁器电路包括优先级系数计算单元，优先级系数比较器，接受确定单元和优先级确定单元。 优先级系数计算单元基于为请求者针对每个请求设置的优先级来为每个请求计算仲裁优先级系数。 优先级系数比较器比较优先级系数计算单元对请求者计算的仲裁优先级系数。 接受确定单元基于优先级系数比较器的比较结果确定是否接受请求。 当由优先级系数计算单元计算的仲裁优先级系数在两个或更多个请求之间相等时，优先级确定单元确定接受请求的优先顺序。

    Arbiter circuit
    2.
    发明授权
    Arbiter circuit 有权
    仲裁电路

    公开(公告)号：US07650451B2

    公开(公告)日：2010-01-19

    申请号：US11790337

    申请日：2007-04-25

    申请人： Tetsuo Miyamoto ,  Yasuhiro Watanabe

    发明人： Tetsuo Miyamoto ,  Yasuhiro Watanabe

    IPC分类号： G06F13/362

    CPC分类号： G06F13/364

    摘要： An arbiter circuit includes a priority coefficient calculating unit, a priority coefficient comparator an acceptance determining unit, and a priority determining unit. The priority coefficient calculating unit calculates for each request an arbitration priority coefficient based on a priority level set for each request by requesters. The priority coefficient comparator compares arbitration priority coefficients calculated for the requesters by the priority coefficient calculating unit. The acceptance determining unit determines whether to accept the requests based on the comparison result by the priority coefficient comparator. When the arbitration priority coefficient calculated by the priority coefficient calculating unit is equal between two or more requests, the priority determining unit determines a priority order for accepting the requests.

    摘要翻译： 仲裁器电路包括优先级系数计算单元，优先级系数比较器，接受确定单元和优先级确定单元。 优先级系数计算单元基于为请求者针对每个请求设置的优先级来为每个请求计算仲裁优先级系数。 优先级系数比较器比较由优先级系数计算单元计算的请求者的仲裁优先级系数。 接受确定单元基于优先级系数比较器的比较结果确定是否接受请求。 当由优先级系数计算单元计算的仲裁优先级系数在两个或更多个请求之间相等时，优先级确定单元确定接受请求的优先顺序。

    NMR probe
    3.
    发明授权
    NMR probe 有权
    NMR探针

    公开(公告)号：US07714579B2

    公开(公告)日：2010-05-11

    申请号：US12129060

    申请日：2008-05-29

    申请人： Hiroto Suematsu ,  Yoshiki Kida ,  Yoshiaki Yamakoshi ,  Hiroshi Ikeda ,  Tetsuo Miyamoto ,  Ryoji Tanaka

    发明人： Hiroto Suematsu ,  Yoshiki Kida ,  Yoshiaki Yamakoshi ,  Hiroshi Ikeda ,  Tetsuo Miyamoto ,  Ryoji Tanaka

    IPC分类号： G01V3/00

    CPC分类号： G01R33/34046 ,  G01R33/34061 ,  G01R33/34092 ,  G01R33/3635

    摘要： An NMR probe permits measurements to be made with its inner coil without replacing the probe. The NMR probe has three coils disposed to surround a sample tube. An inner coil can resonate with the HF and LF. An intermediate coil can resonate with the HF and LF, and produces an RF magnetic field perpendicular to the RF field produced by the inner coil. An outermost coil can resonate at least at a lock frequency. The outermost coil produces an RF magnetic field which is perpendicular to the RF field produced by the intermediate coil but which is coincident in direction with the RF field produced by the inner coil.

    摘要翻译： NMR探头允许使用其内部线圈进行测量，而无需更换探头。 NMR探针具有围绕样品管设置的三个线圈。 内部线圈可以与HF和LF谐振。 中间线圈可以与HF和LF共振，并产生垂直于由内线圈产生的RF场的RF磁场。 最外面的线圈可以至少以锁定频率谐振。 最外面的线圈产生垂直于由中间线圈产生的RF场的RF磁场，但是它与由内线圈产生的RF场方向一致。

    Memory device, memory controller and memory system
    4.
    发明申请
    Memory device, memory controller and memory system 有权
    内存设备，内存控制器和内存系统

    公开(公告)号：US20080151677A1

    公开(公告)日：2008-06-26

    申请号：US11698286

    申请日：2007-01-26

    申请人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

    发明人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

    IPC分类号： G11C8/12

    CPC分类号： G11C11/4087 ,  G09G5/393 ,  G09G5/395 ,  G11C8/12

    摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

    摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

    Data transfer control apparatus and data transfer control method
    5.
    发明授权
    Data transfer control apparatus and data transfer control method 有权
    数据传输控制装置和数据传输控制方法

    公开(公告)号：US08423742B2

    公开(公告)日：2013-04-16

    申请号：US12057533

    申请日：2008-03-28

    申请人： Tetsuo Miyamoto

    发明人： Tetsuo Miyamoto

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1642 ,  G06F7/5306

    摘要： A data transfer control apparatus includes a memory, a write control part controlling data writing to the memory, a read control part controlling data reading from the memory, a read-start calculation part calculating an output timing of a notification which indicates a read-start operation to the read control part based on each transfer condition of the data writing to the memory and the data reading from the memory, and an asynchronous transfer part asynchronously transferring a clock of the notification, and notifying the read control part of the notification.

    摘要翻译： 数据传送控制装置包括存储器，控制对存储器的写入数据的写入控制部分，控制从存储器读取数据的读取控制部分，计算指示读取开始的通知的输出定时的读取开始计算部分 基于对存储器的数据写入的每个传送条件和从存储器读取的数据的读取控制部分的操作，以及异步传送部件异步传送通知的时钟，并通知读取控制部分通知。

    NMR Probe
    7.
    发明申请
    NMR Probe 有权
    NMR探针

    公开(公告)号：US20080297156A1

    公开(公告)日：2008-12-04

    申请号：US12129060

    申请日：2008-05-29

    申请人： Hiroto Suematsu ,  Yoshiki Kida ,  Yoshiaki Yamakoshi ,  Hiroshi Ikeda ,  Tetsuo Miyamoto ,  Ryoji Tanaka

    发明人： Hiroto Suematsu ,  Yoshiki Kida ,  Yoshiaki Yamakoshi ,  Hiroshi Ikeda ,  Tetsuo Miyamoto ,  Ryoji Tanaka

    IPC分类号： G01R33/341

    CPC分类号： G01R33/34046 ,  G01R33/34061 ,  G01R33/34092 ,  G01R33/3635

    摘要： An NMR probe permits measurements to be made with its inner coil without replacing the probe. The NMR probe has three coils disposed to surround a sample tube. An inner coil can resonate with the HF and LF. An intermediate coil can resonate with the HF and LF, and produces an RF magnetic field perpendicular to the RF field produced by the inner coil. An outermost coil can resonate at least at a lock frequency. The outermost coil produces an RF magnetic field which is perpendicular to the RF field produced by the intermediate coil but which is coincident in direction with the RF field produced by the inner coil.

    摘要翻译： NMR探头允许使用其内部线圈进行测量，而无需更换探头。 NMR探针具有围绕样品管设置的三个线圈。 内部线圈可以与HF和LF谐振。 中间线圈可以与HF和LF共振，并产生垂直于由内线圈产生的RF场的RF磁场。 最外面的线圈可以至少以锁定频率谐振。 最外面的线圈产生垂直于由中间线圈产生的RF场的RF磁场，但是它与由内线圈产生的RF场方向一致。

    Memory device, memory controller and memory system
    10.
    发明授权
    Memory device, memory controller and memory system 有权
    内存设备，内存控制器和内存系统

    公开(公告)号：US08015389B2

    公开(公告)日：2011-09-06

    申请号：US12000953

    申请日：2007-12-19

    申请人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

    发明人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

    IPC分类号： G06F12/06

    CPC分类号： G11C11/4087 ,  G09G5/393 ,  G09G5/395 ,  G11C8/12

    摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

    摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。