-
11.发明申请公开(公告)号：US20220405581A1
公开(公告)日：2022-12-22
申请号：US17642972
申请日：2020-12-07
Applicant: Hitachi, Ltd.
Inventor： Tadanobu TOBA , Takumi UEZONO , Kenichi SHIMBO , Hiroaki ITSUJI , Nozomi KASAHARA , Yutaka UEMATSU
Abstract: A neural network that can detect abnormality of itself while suppressing redundancy of a scale is realized. A neural network optimization system includes a definition data analysis unit configured to analyze learned neural network definition data, an internode dependence degree analysis unit configured to generate dependence degree information indicating an internode dependence degree in a learned neural network defined by the learned neural network definition data, based on an analysis result of the learned neural network definition data, and a sensitive node extraction unit configured to extract a sensitive node in the learned neural network based on the dependence degree information.
-
公开(公告)号：US20220261986A1
公开(公告)日：2022-08-18
申请号：US17535779
申请日：2021-11-26
Applicant: Hitachi, Ltd.
Inventor： Takumi UEZONO , Tadanobu TOBA , Kenichi SHIMBO , Hiroaki ITSUJI
Abstract: An increase in a diagnosis load can be reduced. A diagnosis pattern generating unit generates a diagnosis pattern including a plurality of data sets for diagnosing whether a processing result of calculation processing by a subset of a plurality of intermediate nodes included in a learned neural network is correct. An intermediate node calculation component identifying unit identifies a node-core relationship that is a correspondence relationship between the intermediate node and a calculation component that executes calculation processing by the intermediate node. A diagnosis pattern reducing unit reduces the number of the plurality of data sets based on the node-core relationship.
-
公开(公告)号：US20210166422A1
公开(公告)日：2021-06-03
申请号：US17102778
申请日：2020-11-24
Applicant: HITACHI, LTD.
Inventor： Hiroaki ITSUJI , Takumi UEZONO , Tadanobu TOBA , Kenichi SHIMBO , Yutaka UEMATSU
Abstract: To detect a discrimination error in a type of an object. A calculation system includes a first device and a second device. The first device includes: a first object map generation unit configured to calculate, using first image information that is image information acquired by the first device, a first object map indicating a type of an object and a position of the object; and a first communication unit configured to transmit the first object map to the second device. The second device includes: a second object map generation unit configured to calculate, using second image information that is image information acquired by the second device, a second object map indicating a type of an object and a position of the object; and a comparison unit configured to compare the first object map and the second object map.
-
公开(公告)号：US20190332727A1
公开(公告)日：2019-10-31
申请号：US16389332
申请日：2019-04-19
Applicant: HITACHI, LTD.
Inventor： Takumi UEZONO , Tadanobu TOBA , Masahiro SHIRAISHI , Hideo HARADA , Satoshi NISHIKAWA
Abstract: Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.
-
公开(公告)号：US20170350933A1
公开(公告)日：2017-12-07
申请号：US15535219
申请日：2015-04-24
Applicant: HITACHI, LTD.
Inventor： Yutaka UEMATSU , Hideki OSAKA , Tadanobu TOBA , Kenichi SHIMBO
IPC: G01R31/04 , G01R31/28 , H01L23/00 , H01L25/065 , H01L23/498
CPC classification number: G01R31/041 , G01R31/026 , G01R31/2851 , G01R31/2853 , H01L23/49838 , H01L24/16 , H01L25/0655 , H01L25/0657 , H01L2224/13025 , H01L2224/16146 , H01L2224/16227 , H01L2224/1623 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/15192 , H01L2924/15311
Abstract: Provided is a semiconductor inspection circuit which is capable of inspecting connection states of power supply, ground, and signal bumps in a semiconductor package or a printed circuit board equipped with a semiconductor LSI mounted in a product operation state. As a means to solve the problem, a circuit capable of switching a path is provided at an input portion of a driver/receiver, a mechanism capable of transferring an output of a path switching circuit near a receiver circuit to a voltage waveform circuit with an internal variable terminal is provided, and a breakage state of a bump can be observed in the product operation state by observing a DC level at a terminal having a certain DC resistance when a signal bump connection state is observed and receiving a step wave and observing a response waveform thereof when an IO power supply bump connection state is observed.
-
Patent Agency Ranking
公开(公告)号：US20230082529A1
公开(公告)日：2023-03-16
申请号：US17795025
申请日：2020-08-18
Applicant: Hitachi, Ltd.
Inventor： Takumi UEZONO , Masahiro SHIRAISHI , Tadanobu TOBA , Satoshi NISHIKAWA , Keisuke YAMAMOTO
Abstract: The operational continuity of a programmable device, and a controller using the same is enhanced. A programmable device is configured with: an error check mechanism that detects, and notifies an error from redundantized user logic blocks; a previous value retaining section that is connected to an output terminal of a last user logic block, and takes in, and outputs an output value of the user logic blocks in each control period; a CRAM check section that receives a scan interrupt due to an error occurrence notification received from the error check mechanism, reads a scan region on the CRAM, implements error detection, and error correction, and notifies a success or failure of the error correction; and an error handling section that transmits an instruction for retaining a previous output of the user logic blocks to the previous value retaining section when the error occurrence notification is received, transmits an instruction for cancelling previous-value retention to the previous value retaining section, and also transmits a logical reset instruction to a user logic block relevant to an error when a notification of a success of the error correction is received from the CRAM check section.
-
公开(公告)号：US20230016735A1
公开(公告)日：2023-01-19
申请号：US17837656
申请日：2022-06-10
Applicant: Hitachi, Ltd.
Inventor： Hiroaki ITSUJI , Takumi UEZONO , Kenichi SHIMBO , Tadanobu TOBA
Abstract: Provided is a computer capable of reducing a diagnosis load. For each predetermined diagnosis target node among a plurality of nodes in a neural network, a determination processing unit calculates an expected output value expected as a calculation result of a node calculation process corresponding to the predetermined diagnosis target node, which is obtained when the node calculation process is executed using a predetermined input value. For each diagnosis target node, a generation processing unit generates as a diagnosis program a program for comparing the calculation result of the node calculation process corresponding to the diagnosis target node, which is obtained when the node calculation process is executed by an NN calculation processor using the input value, with the expected output value.
-
公开(公告)号：US20220414207A1
公开(公告)日：2022-12-29
申请号：US17642793
申请日：2020-12-07
Applicant: Hitachi, Ltd.
Inventor： Kenichi SHIMBO , Tadanobu TOBA
IPC: G06F21/55
Abstract: Malware infection or an abnormal operation caused by a malicious attack is detected in real time, even in an electronic device with relatively inferior processing capacity. An electronic device includes an executable code identification unit configured to receive an executable code string output from a processor, and identify at least an execution address in a user program region of an operating system (OS), and an execution address in a kernel region, and a determination unit configured to check a predetermined feature value obtained at a predetermined timing from an identification result obtained by the executable code identification unit, against a predetermined expected value, and determine that an attack happens, in a case where a difference is equal to or larger than a predetermined difference, and the determination unit notifies the processor of a predetermined abnormality notification signal if the determination unit determines that an attack happens.
-
公开(公告)号：US20220163942A1
公开(公告)日：2022-05-26
申请号：US17451424
申请日：2021-10-19
Applicant: Hitachi, Ltd.
Inventor： Tadanobu TOBA , Kenichi Shimbo , Yutaka Uematsu , Takumi Uezono
IPC: G05B19/406 , G06F11/34
Abstract: The subject is to provide a technique of dealing with an internal state of a controller in an edge device by cooperation between an edge device and a computer such as a cloud server, and to generalize data communication for the cooperation and reduce an amount of data communication. Provided is a distributed system including an edge device and a diagnostic data computer. The edge device includes an in-edge controller including at least a processing unit, and a system element to be monitored by the in-edge controller. The processing unit diagnoses presence or absence of an abnormality in the processing unit due to an abnormality occurring in the system element, generates first diagnostic data indicating presence or absence of the abnormality of the processing unit, converts the first diagnostic data into second diagnostic data indicating a type of the abnormality of the processing unit, and transmits the second diagnostic data to the diagnostic data computer.
-
公开(公告)号：US20210357285A1
公开(公告)日：2021-11-18
申请号：US17246940
申请日：2021-05-03
Applicant: Hitachi, Ltd.
Inventor： Hiroaki ITSUJI , Takumi UEZONO , Kenichi SHIMBO , Tadanobu TOBA
Abstract: A program for causing a parallel arithmetic device including a plurality of arithmetic groups to execute parallel arithmetic is input. The program includes information defining each of the following: application arithmetic constituting predetermined processing; redundant arithmetic (which is redundant arithmetic of the application arithmetic and is arithmetic assigned to a surplus core(s) in a diagnosis target arithmetic group); and diagnostic arithmetic (arithmetic that is a comparison of results of the same redundant arithmetic by two or more diagnosis target arithmetic groups and is assigned to surplus cores in an arithmetic group for diagnosis). The surplus core(s) is a core(s) to which no application arithmetic is assigned.
-
-
-
-
-
-
-
-
-
Search Results
24
records
(took 0.015 seconds)
