公开(公告)号：US20220027292A1

公开(公告)日：2022-01-27

申请号：US17498348

申请日：2021-10-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Victor Gissin ,  Junying Li ,  Guanfeng Zhou ,  Jiashu Lin

IPC: G06F13/16 ,  G06F9/50 ,  G06F13/362 ,  G06F13/42

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

公开(公告)号：US10572340B2

公开(公告)日：2020-02-25

申请号：US15585858

申请日：2017-05-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Guanfeng Zhou

IPC: G11C29/00 ,  G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G06F21/64 ,  G11C29/52 ,  G06F21/60

Abstract: A method for managing a solid state disk (SSD) storage device and accessing data of the SSD storage device in order to resolve problems of highly complex data management in an SDD and different service lives of NAND flash physical pages in a NAND flash physical block where, lengths of a user data area, primary metadata, and an error checking and correction (ECC) code in each storage unit of an SSD storage device are set to fixed values. As a result, a format of data stored in the storage unit is fixed, and the ECC code can also ensure consistency between data in the user data area and the primary metadata at a fixed code rate in order to ensure correctness and integrity of the data in the user data area and the primary metadata.

公开(公告)号：US20190146689A1

公开(公告)日：2019-05-16

申请号：US16242566

申请日：2019-01-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Guanfeng Zhou

IPC: G06F3/06 ,  G11C16/34 ,  G11C29/52 ,  G11C16/26 ,  G06F11/10

Abstract: A flash device access method, apparatus, and system, where a flash device includes a controller and a storage array. The method includes dividing the storage array into a specific storage unit and a user storage unit, such that a storage feature of the specific storage unit is the same as that of the user storage unit, writing, by the controller, specific data into the specific storage unit, reading, by the controller, the specific data stored in the specific storage unit, determining, by the controller, a decision voltage (Vread) based on the read specific data, and reading, by the controller using the determined Vread, the user data stored in the user storage unit. Hence, incorrect determining of the data stored in the flash device may be reduced using the access method, apparatus, and system.

公开(公告)号：US20230409198A1

公开(公告)日：2023-12-21

申请号：US18460608

申请日：2023-09-04

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yigang Zhou ,  Xiaoming Zhu ,  Guanfeng Zhou

IPC: G06F3/06 ,  G06F9/50

CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/067 ,  G06F9/5016

Abstract: In a computer device, a memory sharing control device is deployed between a processor and a memory pool, and the processor accesses the memory pool via the memory sharing control device. Different processing units, such as processors or cores in processors, access one memory in the memory pool in different time periods, so that the memory is shared by a plurality of processing units, and utilization of memory resources is improved.

公开(公告)号：US10725673B2

公开(公告)日：2020-07-28

申请号：US16242566

申请日：2019-01-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Guanfeng Zhou

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/28 ,  G06F11/10 ,  G11C29/52

Abstract: A flash device access method, apparatus, and system, where a flash device includes a controller and a storage array. The method includes dividing the storage array into a specific storage unit and a user storage unit, such that a storage feature of the specific storage unit is the same as that of the user storage unit, writing, by the controller, specific data into the specific storage unit, reading, by the controller, the specific data stored in the specific storage unit, determining, by the controller, a decision voltage (Vread) based on the read specific data, and reading, by the controller using the determined Vread, the user data stored in the user storage unit. Hence, incorrect determining of the data stored in the flash device may be reduced using the access method, apparatus, and system.

公开(公告)号：US20200065264A1

公开(公告)日：2020-02-27

申请号：US16673320

申请日：2019-11-04

Applicant: Huawei Technologies Co., Ltd.

Inventor： Victor Gissin ,  Junying Li ,  Guanfeng Zhou ,  Jiashu Lin

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/362 ,  G06F9/50

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

公开(公告)号：US20170228330A1

公开(公告)日：2017-08-10

申请号：US15422779

申请日：2017-02-02

Applicant: Huawei Technologies Co., Ltd.

Inventor： Rui Huang ,  Zhi Zhang ,  Guanfeng Zhou

IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F13/4081 ,  G06F13/4282

Abstract: A hot swappable device includes a port, a firmware module, and an interrupt masking module. The port includes a Peripheral Component Interface express Physical Layer, and the Peripheral Component Interface express Physical Layer includes multiple lanes lanes. The Peripheral Component Interface express Physical Layer detects an analog signal in each of the multiple lanes, when it is detected that an amplitude of an analog signal in one of the multiple lanes is less than a preset threshold, generates an ALOS signal corresponding to the lane, and transmits the ALOS signal to the interrupt masking module. The interrupt masking module generates an ALOS interrupt signal corresponding to the lane and sends the ALOS interrupt signal to the firmware module. If the firmware module receives, in a preset time period, an ALOS interrupt signal corresponding to each lane, the firmware module resets the port.