公开(公告)号：US20240154699A1

公开(公告)日：2024-05-09

申请号：US18416436

申请日：2024-01-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Changzheng Su ,  Lei Zhao ,  Yigang Zhou

IPC: H04B10/2507 ,  H04B10/40

CPC classification number: H04B10/2507 ,  H04B10/40 ,  H04B2210/006

Abstract: An optical/electrical module includes an analog equalizer and an optical/electrical conversion unit. The analog equalizer is connected to the optical/electrical conversion unit. The analog equalizer is configured to: perform first analog signal equalization processing on a first electrical signal to obtain a second electrical signal, and send the second electrical signal to the optical/electrical conversion unit, or is configured to: receive a third electrical signal from the optical/electrical conversion unit, and perform second analog signal equalization processing on the third electrical signal to obtain a fourth electrical signal. The optical/electrical conversion unit is configured to: receive the second electrical signal from the analog equalizer and convert the second electrical signal into a first optical signal. According to embodiments of this application, equalization processing may be performed on an electrical signal in an analog domain.

公开(公告)号：US20240086244A1

公开(公告)日：2024-03-14

申请号：US18515471

申请日：2023-11-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yigang Zhou ,  Yongnian Le ,  Haicheng Li ,  Kebing Wang

IPC: G06F9/50

CPC classification number: G06F9/5027

Abstract: A scheduling method performed by a computing device that includes a plurality of processors, a type of at least one instruction set of instruction sets supported by at least one of the plurality of processors is different from a type of an instruction set of instruction sets supported by another processor, where the scheduling method includes obtaining a type of an instruction set of an application, selecting a target processor from the plurality of processors, where the type of the instruction set of the application is a subset of types of a plurality of instruction sets of instruction sets supported by the target processor, and allocating the application to the target processor for execution.

公开(公告)号：US20220404973A1

公开(公告)日：2022-12-22

申请号：US17896884

申请日：2022-08-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiaoming Zhu ,  Yigang Zhou

IPC: G06F3/06

Abstract: This application discloses a data processing method for a memory device, an apparatus, and a system, and relates to the field of data storage technologies, so that memory capacity expansion can be implemented, and the memory capacity expansion is not limited by an original quantity of DDR channels. The memory device includes a controller, a first memory, and a second memory, the controller separately communicates with a processor, the first memory, and the second memory, and read/write performance of the first memory is higher than read/write performance of the second memory. The method includes receiving an operation request of the processor, where the operation request includes a logical address, and accessing the first memory or the second memory based on the logical address.

公开(公告)号：US20240338328A1

公开(公告)日：2024-10-10

申请号：US18744042

申请日：2024-06-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wen Yin ,  Wei Li ,  Yigang Zhou ,  Manbo Wu ,  Xianzhou Lin ,  Chuanwei Wen ,  Ruonan Wang ,  Yining Li

IPC: G06F13/16 ,  G06F13/18 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F13/18 ,  G06F13/409 ,  G06F13/4243

Abstract: A data processing system includes a computing subsystem and a memory subsystem. In the computing subsystem, a processor is connected to one end of a high-speed parallel bus via a first bus interface. The processor transmits data to the memory subsystem and receives data transmitted through the high-speed parallel bus. The memory subsystem receives and transmits data to the computing subsystem through the high-speed parallel bus.

公开(公告)号：US20230409198A1

公开(公告)日：2023-12-21

申请号：US18460608

申请日：2023-09-04

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yigang Zhou ,  Xiaoming Zhu ,  Guanfeng Zhou

IPC: G06F3/06 ,  G06F9/50

CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/067 ,  G06F9/5016

Abstract: In a computer device, a memory sharing control device is deployed between a processor and a memory pool, and the processor accesses the memory pool via the memory sharing control device. Different processing units, such as processors or cores in processors, access one memory in the memory pool in different time periods, so that the memory is shared by a plurality of processing units, and utilization of memory resources is improved.