公开(公告)号：US11200949B2

公开(公告)日：2021-12-14

申请号：US16971678

申请日：2019-07-12

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Xiangshui Miao ,  Yi Li ,  Xiaodi Huang

IPC: G11C11/00 ,  G11C13/00 ,  G06F7/523 ,  G11C7/10

Abstract: The invention discloses a multiplier and an operation method based on 1T1R memory. The multiplier includes: a 1T1R crossbar A1, a 1T1R crossbar A2, a 1T1R crossbar A3, and a peripheral circuit. The 1T1R matrices are configured to realize operation and store result of it, and the peripheral circuit is configured to transfer data and control signals, thereby controlling the operation and storage process of the 1T1R matrices. An operation circuit is configured to respectively achieve NOR Boolean logic operations, two-bit binary multipliers, and optimization. The operation method corresponding to the operation circuit respectively completes the corresponding calculation and storage process by controlling an initialization resistance state of 1T1R devices, the size of a word line input signal, the size of a bit line input signal, and the size of a source line input signal.

公开(公告)号：US11171650B2

公开(公告)日：2021-11-09

申请号：US16965602

申请日：2019-07-16

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Yi Li ,  Long Cheng ,  Xiangshui Miao

IPC: H03K19/177 ,  H03K19/173

Abstract: A reversible logic circuit and an operation method thereof are provided. The logic circuit includes resistive switching cells, word lines, and bit lines. The word lines and the bit lines are perpendicular to each other. The anode of a resistive switching cell is connected to the word line as a first input terminal to apply logic operating voltage or be grounded. The cathode of a resistive switching cell is connected to the bit line as a second input terminal to apply logic operating voltage or be grounded. When performing reversible logic operation, four levels of resistance states of the resistive switching cell are used as logic outputs to implement single-input NOT and dual-input C-NOT reversible logic functions.

公开(公告)号：US10020054B2

公开(公告)日：2018-07-10

申请号：US15629714

申请日：2017-06-21

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Qun Liu ,  Tao Zhang ,  Xiangshui Miao ,  Yi Li ,  Yaxiong Zhou ,  Tianpeng Miao

IPC: G06F12/0813 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2213/77

Abstract: A processor including a computing and memory structure including X in number integration units and X in number communication units, and a control unit. The integration units are computing and memory units (CMUs), each computing and memory unit (CMU) is connected to a corresponding communication unit. The control unit is configured to produce control signals according to the commands, connect communication networks between the CMUs, choose operand addresses and result storage addresses, and search for one or a plurality of idle CMUs when extra CMUs are required for an operation. Each computing and memory unit includes M in number bit units and M−1 in number vertical line switches. Each bit unit includes a resistor, a horizontal line switch and N in number memristors. X is a positive integer greater than or equal to 2; M is a positive integer greater than or equal to 1.