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公开(公告)号：US11475949B2
公开(公告)日：2022-10-18
申请号：US16336900
申请日：2018-06-07
发明人： Yi Li , Zhuorui Wang , Xiangshui Miao , Yaxiong Zhou , Long Cheng
摘要： The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.
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公开(公告)号：US11171650B2
公开(公告)日：2021-11-09
申请号：US16965602
申请日：2019-07-16
发明人： Yi Li , Long Cheng , Xiangshui Miao
IPC分类号： H03K19/177 , H03K19/173
摘要： A reversible logic circuit and an operation method thereof are provided. The logic circuit includes resistive switching cells, word lines, and bit lines. The word lines and the bit lines are perpendicular to each other. The anode of a resistive switching cell is connected to the word line as a first input terminal to apply logic operating voltage or be grounded. The cathode of a resistive switching cell is connected to the bit line as a second input terminal to apply logic operating voltage or be grounded. When performing reversible logic operation, four levels of resistance states of the resistive switching cell are used as logic outputs to implement single-input NOT and dual-input C-NOT reversible logic functions.
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