公开(公告)号：US11645503B2

公开(公告)日：2023-05-09

申请号：US16723131

申请日：2019-12-20

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Mohit Gupta ,  Bharani Chakravarthy Chava ,  Wim Dehaene ,  Sushil Sakhare

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/04 ,  G11C11/54

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06N3/04 ,  G11C11/54

Abstract: A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.

公开(公告)号：US20210193912A1

公开(公告)日：2021-06-24

申请号：US17119010

申请日：2020-12-11

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Mohit Gupta ,  Trong Huynh Bao

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32

Abstract: A material layer stack, a non-volatile memory device comprising the stack, and arrays thereof are described. The material layer stack comprises first and second magnetic tunnel junctions and a first top electrode formed on a top face of the stack. A shoulder is formed on a lateral face of the stack and divides the stack into a lower portion and an upper portion, wherein a tunnel barrier of the first magnetic tunnel junction is comprised by the lower stack portion and a tunnel barrier of the second magnetic tunnel junction by the upper stack portion. A second top electrode is formed on the shoulder. Each magnetic tunnel junction is adapted to store a bit as a reconfigurable magnetoresistance of its magnetic electrodes. Preferably, a bottom face of the stack is connected to a conductor supporting current induced magnetic polarization switching for the first magnetic tunnel junction by spin-orbit torque; magnetic polarization switching for the second magnetic tunnel junction is preferably achieved by spin-transfer torque.

公开(公告)号：US11004490B2

公开(公告)日：2021-05-11

申请号：US16716024

申请日：2019-12-16

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Sushil Sakhare ,  Kevin Garello ,  Mohit Gupta ,  Manu Komalan Perumkunnil

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: The disclosed technology relates generally to magnetic random access memory, and more particularly to spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM). According to an aspect, a MRAM device comprises a first transistor, a second transistor, and a resistive memory element. The resistive memory element comprises a magnetic tunnel junction (MTJ) pillar arranged between a top electrode and bottom electrode having a first terminal and a second terminal. According to another aspect, a method of using the MRAM device is disclosed.

公开(公告)号：US20240107739A1

公开(公告)日：2024-03-28

申请号：US18472122

申请日：2023-09-21

Applicant: IMEC VZW

Inventor： Nouredine Rassoul ,  Hyungrock Oh ,  Romain Delhougne ,  Gouri Sankar Kar ,  Attilio Belmonte ,  Kaustuv Banerjee ,  Mohit Gupta

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A memory device configured as a dynamic random access memory is provided, comprising a first semiconductor device layer comprising a first bit cell and a second semiconductor device layer comprising a second DRAM bit cell. Further, at least one of a first and second interconnecting structure is provided, the first interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a write word line common to the gate terminal of the write transistors of the first and second bit cells, and the second interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a read word line common to a first source/drain terminal of the read transistors of the first and second bit cells.