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    STRUCTURE FOR A FIELD EFFECT TRANSISTOR (FET) DEVICE AND METHOD OF PROCESSING A FET DEVICE
    2.
    发明申请
    STRUCTURE FOR A FIELD EFFECT TRANSISTOR (FET) DEVICE AND METHOD OF PROCESSING A FET DEVICE 有权

    公开(公告)号：US20220020882A1

    公开(公告)日：2022-01-20

    申请号：US17305797

    申请日：2021-07-14

    Applicant: IMEC vzw

    Inventor： Nouredine Rassoul ,  Romain Delhougne ,  Attilio Belmonte ,  Gouri Sankar Kar

    IPC: H01L29/786 ,  H01L29/66 ,  H01L23/00 ,  H01L29/24 ,  H01L29/10

    Abstract: The disclosed technology generally relates to a structure for a field effect transistor (FET) device and a method of processing a FET device. In one aspect, the method can include providing a substrate, forming an oxygen passing layer on the substrate, and forming an oxygen blocking layer on the substrate. The oxygen blocking layer can be arranged next to the oxygen passing layer and can delimit the oxygen passing layer on two opposite sides. The method can also include forming an oxide semiconductor layer on the oxygen passing layer and the oxygen blocking layer, forming a gate structure on the oxide semiconductor layer in a region above the oxygen passing layer, and modifying a doping of the oxide semiconductor layer by introducing oxygen into the oxygen passing layer. At least a portion of the introduced oxygen can pass through the oxygen passing layer and into the oxide semiconductor layer.

    DYNAMIC RANDOM-ACCESS MEMORY DEVICE AND METHOD OF FABRICATING SAME
    5.
    发明公开
    DYNAMIC RANDOM-ACCESS MEMORY DEVICE AND METHOD OF FABRICATING SAME 审中-公开

    公开(公告)号：US20240107739A1

    公开(公告)日：2024-03-28

    申请号：US18472122

    申请日：2023-09-21

    Applicant: IMEC VZW

    Inventor： Nouredine Rassoul ,  Hyungrock Oh ,  Romain Delhougne ,  Gouri Sankar Kar ,  Attilio Belmonte ,  Kaustuv Banerjee ,  Mohit Gupta

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A memory device configured as a dynamic random access memory is provided, comprising a first semiconductor device layer comprising a first bit cell and a second semiconductor device layer comprising a second DRAM bit cell. Further, at least one of a first and second interconnecting structure is provided, the first interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a write word line common to the gate terminal of the write transistors of the first and second bit cells, and the second interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a read word line common to a first source/drain terminal of the read transistors of the first and second bit cells.

    Method for Operating a Conductive Bridging Memory Device
    6.
    发明申请
    Method for Operating a Conductive Bridging Memory Device 有权
    用于操作导电桥接存储器件的方法

    公开(公告)号：US20160155502A1

    公开(公告)日：2016-06-02

    申请号：US14957249

    申请日：2015-12-02

    Applicant: Katholieke Universiteit Leuven, KU LEUVEN R&D ,  IMEC VZW

    Inventor： Ludovic Goux ,  Attilio Belmonte

    IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C11/56

    CPC classification number: G11C13/0069 ,  G11C11/5614 ,  G11C13/0011 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2013/0092 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146

    Abstract: A method is disclosed for operating a Conductive Bridge Random Access Memory (CBRAM) device that includes an electrolyte element sandwiched between a cation supply top electrode and a bottom electrode. The method comprises conditioning the CBRAM device by applying a forming current pulse having a pulse width (tf) of 100 ns or less and a pulse amplitude (If) of 10 uA or less, and when programming, setting the conditioned CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (ts) of 100 ns or less and a pulse amplitude (Is) equal to or larger than the forming current pulse amplitude (If).

    Abstract translation: 公开了一种用于操作导电桥随机存取存储器（CBRAM）器件的方法，该器件包括夹在阳离子供应顶电极和底电极之间的电解质元件。 该方法包括通过施加具有100ns或更小的脉冲宽度（tf）和10uA或更小的脉冲幅度（If）的形成电流脉冲来调节CBRAM器件，并且当编程时，将经调节的CBRAM器件设置为低 通过施加具有100ns以下的脉冲宽度（ts）的设定电流脉冲和等于或大于成形电流脉冲振幅（If）的脉冲幅度（Is）的电阻状态（LRS）。

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