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    Dual magnetic tunnel junction stack
    3.
    发明授权
    Dual magnetic tunnel junction stack 有权

    公开(公告)号：US11832525B2

    公开(公告)日：2023-11-28

    申请号：US17119010

    申请日：2020-12-11

    Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

    Inventor： Mohit Gupta ,  Trong Huynh Bao

    IPC: H10N50/10 ,  G11C11/16 ,  H01F10/32 ,  H10N50/80 ,  H10N50/85

    CPC classification number: H10N50/10 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/329 ,  H01F10/3286 ,  H10N50/80 ,  H10N50/85

    Abstract: The material layer stack includes first and second magnetic tunnel junctions and a first top electrode formed on a top face of the stack. A shoulder is formed on a lateral face of the stack and divides the stack into a lower portion and an upper portion. A tunnel barrier of the first magnetic tunnel junction is comprised by the lower stack portion and a tunnel barrier of the second magnetic tunnel junction by the upper stack portion. A second top electrode is formed on the shoulder. Each magnetic tunnel junction is adapted to store a bit as a reconfigurable magnetoresistance of its magnetic electrodes. Preferably, a bottom face of the stack is connected to a conductor supporting current induced magnetic polarization switching for the first magnetic tunnel junction by spin-orbit torque. Magnetic polarization switching for the second magnetic tunnel junction is preferably achieved by spin-transfer torque.

    NON-VOLATILE STATIC RANDOM ACCESS MEMORY
    4.
    发明申请
    NON-VOLATILE STATIC RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20210158859A1

    公开(公告)日：2021-05-27

    申请号：US16951919

    申请日：2020-11-18

    Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

    Inventor： Mohit Gupta ,  Manu Komalan Perumkunnil

    IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4076 ,  G11C5/06

    Abstract: The disclosed technology relates to a non-volatile (NV) static random-access memory (SRAM) device, and to a method of operating the same. The NV-SRAM device includes a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell; a first bit-line connected via a first access element to the SRAM bit-cell; a NV bit-cell connected via a switch to the SRAM bit-cell; and a second bit-line connected via a second access element to the NV bit-cell. The NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and respectively from the second bit-line into the NV bit-cell through the second access element.

    Multibit Neural Network
    5.
    发明申请
    Multibit Neural Network 审中-公开

    公开(公告)号：US20200210822A1

    公开(公告)日：2020-07-02

    申请号：US16723131

    申请日：2019-12-20

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

    Inventor： Mohit Gupta ,  Bharani Chakravarthy Chava ,  Wim Dehaene ,  Sushil Sakhare

    IPC: G06N3/063 ,  G11C11/54 ,  G06N3/04 ,  G06F7/544

    Abstract: A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.

    DISTRIBUTED WRITE DRIVER FOR MEMORY ARRAY
    6.
    发明公开
    DISTRIBUTED WRITE DRIVER FOR MEMORY ARRAY 审中-公开

    公开(公告)号：US20240170051A1

    公开(公告)日：2024-05-23

    申请号：US18515812

    申请日：2023-11-21

    Applicant: IMEC VZW

    Inventor： Mohit Gupta

    IPC: G11C11/4096 ,  G11C5/06 ,  G11C11/4076

    CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C11/4076

    Abstract: The disclosed technology relates to a write driver and a method for operating the write driver for a memory device. The write driver is connected to a memory line of the memory device. Multiple memory cells of the memory device are connected to the memory line at different distances from the write driver. The operating method comprises controlling the write driver to provide a smaller amount of current for accessing a first memory cell of the memory cells, and controlling the write driver to provide a larger amount of current for accessing a second memory cell of the memory cells. Thereby, the first memory cell is connected to the memory line at a smaller distance to the write driver than the second memory cell.

    WRITE-READ CIRCUIT WITH A BIT LINE MULTIPLEXER FOR A MEMORY DEVICE
    7.
    发明公开
    WRITE-READ CIRCUIT WITH A BIT LINE MULTIPLEXER FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240170034A1

    公开(公告)日：2024-05-23

    申请号：US18514100

    申请日：2023-11-20

    Applicant: IMEC VZW

    Inventor： Mohit Gupta ,  Stefan Cosemans

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1673

    Abstract: A memory device with multiplexers for multiplexing write and read operations to bit lines is provided. In one aspect, a write-read circuit includes a multiplexer for multiplexing the write and read operations. The multiplexer includes a plurality of select devices, each select device being associated with one of a plurality of bit lines, and each select device including a first transistor and a second transistor. The write-read circuit further includes a controller configured to, for a write operation using a particular bit line, control the multiplexer to turn on both transistors of the first select device associated with the particular bit line, and for a read operation using the particular bit line, control the multiplexer to turn on the first transistor and turn off the second transistor of the first select device associated with the particular bit line.

    SOT multibit memory cell
    9.
    发明授权
    SOT multibit memory cell 有权

    公开(公告)号：US11527709B2

    公开(公告)日：2022-12-13

    申请号：US17027525

    申请日：2020-09-21

    Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

    Inventor： Mohit Gupta ,  Trong Huynh Bao

    IPC: H01L43/08 ,  G01R33/09 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10

    Abstract: The disclosed technology relates to a multibit memory cell. In one aspect, the multibit memory cell includes a plurality of spin-orbit torque (SOT) tracks, plurality of magnetic tunnel junctions (MTJs), an electrically conductive path connecting a first MTJ and a second MTJ together, and a plurality of terminals. The plurality of terminals can be configured to provide a first SOT write current to the first MTJ, a second SOT write current to the second MTJ, and at least one of: the second SOT write current to a third MTJ, a third SOT write current to the third MTJ, and a spin transfer torque (STT) write current through the third MTJ. The junction resistances of the various MTJs are such that a combined multibit memory state of the MTJs is readable by a read current through all the MTJs in series.

    SOT MULTIBIT MEMORY CELL
    10.
    发明申请
    SOT MULTIBIT MEMORY CELL 有权

    公开(公告)号：US20210098694A1

    公开(公告)日：2021-04-01

    申请号：US17027525

    申请日：2020-09-21

    Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

    Inventor： Mohit Gupta ,  Trong Huynh Bao

    IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  G01R33/09

    Abstract: The disclosed technology relates to a multibit memory cell. In one aspect, the multibit memory cell includes a plurality of spin-orbit torque (SOT) tracks, including at least a first SOT track and a second SOT track separate from the first SOT track. The cell further includes a plurality of magnetic tunnel junctions (MTJs), including at least a first MTJ arranged on the first SOT track, and a second MTJ and a third MTJ arranged on the second SOT track. The cell further includes an electrically conductive path connecting the first MTJ and the second MTJ together, and a plurality of terminals, of which some may be optional. The plurality of terminals can be configured to provide a first SOT write current to the first MTJ, a second SOT write current to the second MTJ, and at least one of: the second SOT write current to the third MTJ, a third SOT write current to the third MTJ, and an spin transfer torque (STT) write current through the third MTJ. The junction resistances of the various MTJs are such that a combined multibit memory state of the MTJs is readable by a read current through all the MTJs in series.

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