公开(公告)号：US11322390B2

公开(公告)日：2022-05-03

申请号：US16844845

申请日：2020-04-09

Applicant: IMEC vzw

Inventor： Amey Mahadev Walke ,  Niamh Waldron ,  Nadine Collaert ,  Ming Zhao

IPC: H01L25/16 ,  H01L21/762 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423

Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.

公开(公告)号：US10818491B2

公开(公告)日：2020-10-27

申请号：US16423274

申请日：2019-05-28

Applicant: IMEC VZW

Inventor： Ming Zhao ,  Weiming Guo

IPC: H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L29/15 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: According to an aspect of the present disclosure, there is provided a III-N semiconductor structure comprising: a semiconductor-on-insulator substrate; a buffer structure comprising a superlattice including at least a first superlattice block and a second superlattice block formed on the first superlattice block, the first superlattice block including a repetitive sequence of first superlattice units, each first superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, the second superlattice block including a repetitive sequence of second superlattice units, each second superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, wherein an average aluminum content of the second superlattice block is greater than an average aluminum content of the first superlattice block; and a III-N semiconductor channel layer arranged on the buffer structure.

公开(公告)号：US20180212025A1

公开(公告)日：2018-07-26

申请号：US15817343

申请日：2017-11-20

Applicant: IMEC VZW

Inventor： Ming Zhao

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L21/02

CPC classification number: H01L29/152 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207

Abstract: The present disclosure relates to a III-N based substrate for power electronic devices, comprising a base substrate, a III-N laminate above the base substrate and a buffer layer structure between the base substrate and the III-N laminate. The buffer layer structure comprises at least a first superlattice laminate and a second superlattice laminate above the first superlattice laminate. The first superlattice laminate comprises a repetition of a first superlattice unit which consists of a plurality of first AlGaN layers. The second superlattice laminate comprises a repetition of a second superlattice unit which consists of a plurality of second AlGaN layers. An average aluminum content of the first superlattice laminate is a predetermined difference greater than an average aluminum content of the second superlattice laminate, to improve the vertical breakdown voltage. The present disclosure also relates to a method for manufacturing a III-N based substrate for power electronic devices.