公开(公告)号：US20210358748A1

公开(公告)日：2021-11-18

申请号：US17323540

申请日：2021-05-18

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Niamh Waldron ,  Amey Mahadev Walke ,  Bernardette Kunert ,  Yves Mols

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/778 ,  H01L29/66

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

公开(公告)号：US20210151593A1

公开(公告)日：2021-05-20

申请号：US16950519

申请日：2020-11-17

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  AliReza Alian ,  Uthayasankaran Peralagu

IPC: H01L29/778 ,  H01L29/66

Abstract: A method comprising: providing a semiconductor structure including: a channel, a barrier, a non-conductive structure over the barrier, the non-conductive structure including a cavity having sidewalls separated by a first distance, providing a first non-conductive layer conformally over the non-conductive structure, thereby covering the sidewalls and the bottom surface of the cavity, etching the first non-conductive layer in such a way that it is removed from at least part of the bottom surface but still covers the sidewalls, etching through the bottom surface at most until the channel is reached, by using the first non-conductive layer covering the sidewalls as a mask, thereby forming an opening in the bottom surface of the non-conductive structure, the opening having sidewalls separated by a second distance, smaller than the first distance, and completely removing the first non-conductive layer.

公开(公告)号：US11004962B2

公开(公告)日：2021-05-11

申请号：US16552468

申请日：2019-08-27

Applicant: IMEC vzw

Inventor： Robert Langer ,  Niamh Waldron ,  Bernardette Kunert

IPC: H01L29/08 ,  H01L29/737 ,  H01L21/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66

Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.

公开(公告)号：US20200328108A1

公开(公告)日：2020-10-15

申请号：US16844845

申请日：2020-04-09

Applicant: IMEC vzw

Inventor： Amey Mahadev Walke ,  Niamh Waldron ,  Nadine Collaert ,  Ming Zhao

IPC: H01L21/762 ,  H01L29/778 ,  H01L29/66 ,  H01L25/16

Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.

公开(公告)号：US10340188B2

公开(公告)日：2019-07-02

申请号：US15687304

申请日：2017-08-25

Applicant: IMEC VZW

Inventor： Yves Mols ,  Niamh Waldron ,  Bernardette Kunert

IPC: H01L21/78 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/762 ,  H01L21/683 ,  H01L21/02

Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.

公开(公告)号：US11646200B2

公开(公告)日：2023-05-09

申请号：US17323540

申请日：2021-05-18

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Niamh Waldron ,  Amey Mahadev Walke ,  Bernardette Kunert ,  Yves Mols

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/02395 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02398 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7787

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

公开(公告)号：US20200091003A1

公开(公告)日：2020-03-19

申请号：US16550085

申请日：2019-08-23

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters ,  Niamh Waldron ,  Robert Langer ,  Bernardette Kunert

IPC: H01L21/8258 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/423 ,  H01L21/308 ,  H01L21/3105

Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.

公开(公告)号：US10566250B2

公开(公告)日：2020-02-18

申请号：US16271626

申请日：2019-02-08

Applicant: IMEC vzw

Inventor： Bernardette Kunert ,  Niamh Waldron ,  Weiming Guo

IPC: H01L29/66 ,  H01L21/8258 ,  H01L21/84 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/8252 ,  H01L27/12 ,  H01L29/423

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface. The semiconductor device further includes a first vertical channel layer laterally interposed between and in contact with the dielectric layer and the dielectric filling layer at a first side of the dielectric filling layer, wherein the first vertical channel layer extends above the common top surface.

公开(公告)号：US20150279947A1

公开(公告)日：2015-10-01

申请号：US14671134

申请日：2015-03-27

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L29/41 ,  H01L29/423 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及栅极全能半导体器件及其制造方法。 一方面，该方法包括在STI区域之间的半导体衬底上提供由源区域和漏极区域锚定的至少一个悬浮纳米结构。 悬浮的纳米结构由与半导体衬底的结晶半导体材料不同的结晶半导体材料形成。 一个栅极叠层围绕至少一个悬浮的纳米结构。

公开(公告)号：US20150279725A1

公开(公告)日：2015-10-01

申请号：US14673517

申请日：2015-03-30

Applicant: IMEC VZW

Inventor： Niamh Waldron

IPC: H01L21/762 ,  H01L29/161 ,  H01L21/84 ,  H01L29/06 ,  H01L29/34 ,  H01L29/16 ,  H01L29/201

CPC classification number: H01L21/76251 ,  C12N15/8201 ,  C12N15/8241 ,  C12N15/8261 ,  H01L21/76264 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L29/34 ,  Y02A40/146

Abstract: The disclosed technology generally relates to semiconductor-on-insulator (SOI) devices and more particularly to SOI devices having a channel region comprising a Group III-V or a Group IV semiconductor material, and also relates to methods of fabricating the same. In one aspect, a method comprises providing a pre-patterned donor wafer, providing a handling wafer and bonding the pre-patterned donor wafer to the handling wafer by contacting the first oxide layer to the handling wafer. Providing a pre-patterned donor wafer comprises providing a donor substrate comprising a first semiconductor material, forming shallow trench isolation (STI) regions in the donor substrate, and forming fins in the donor substrate in between the STI regions, where each fin comprises a Group III-V or Group IV semiconductor material that is different from the first semiconducting material and laterally extends in a direction parallel to a major surface of the donor substrate and between the STI regions. Providing the pre-patterned donor wafer additionally includes providing a first oxide layer overlying the STI regions and the fins. After bonding the donor wafer to the handling wafer, at least part of the first semiconducting material of the pre-patterned donor wafer is removed and the STI regions and the fins are thinned thereby forming channel regions comprising the Group III-V or Group IV semiconductor material.

Abstract translation: 所公开的技术通常涉及绝缘体上半导体（SOI）器件，更具体地涉及具有包含III-V族或IV族半导体材料的沟道区的SOI器件，并且还涉及其制造方法。 在一个方面，一种方法包括提供预先构图的施主晶片，提供处理晶片，并通过使第一氧化物层与处理晶片接触来将预构图的施主晶片连接到处理晶片。 提供预构图的施主晶片包括提供包括第一半导体材料的施主衬底，在施主衬底中形成浅沟槽隔离（STI）区域，以及在STI区域之间在施主衬底中形成鳍，其中每个鳍包括组 III-V或IV族半导体材料，其不同于第一半导体材料并且在平行于施主衬底的主表面和STI区域的主表面的方向上横向延伸。 提供预构图施主晶片另外包括提供覆盖STI区域和鳍片的第一氧化物层。 在将施主晶片结合到处理晶片之后，去除预构图施主晶片的至少一部分第一半导体材料，并且使STI区域和鳍片变薄从而形成包括III-V族或IV族半导体的沟道区 材料。