公开(公告)号：US10930750B2

公开(公告)日：2021-02-23

申请号：US16222911

申请日：2018-12-17

Applicant: IMEC vzw

Inventor： Clement Merckling ,  Nadine Collaert

IPC: H01L39/14 ,  H01L29/43 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/41 ,  H01L29/76 ,  G06N10/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3205 ,  H01L29/417 ,  H01L29/786

Abstract: The disclosed technology is directed to a method of forming a qubit device. In one aspect, the method comprises: forming a gate electrode embedded in an insulating layer formed on a substrate, wherein an upper surface of the substrate is formed from a group IV semiconductor material and the gate electrode extends along the substrate in a first horizontal direction; forming an aperture in the insulating layer, the aperture exposing a portion of the substrate; forming, in an epitaxial growth process, a semiconductor structure comprising a group III-V semiconductor substrate contact part and a group III-V semiconductor disc part, the substrate contact part having a bottom portion abutting the portion of the substrate and an upper portion protruding from the aperture above an upper surface of the insulating layer, the semiconductor disc part extending from the upper portion of the substrate contact part, horizontally along the upper surface of the insulating layer to overlap a portion of the gate electrode; forming a mask covering a portion of the disc part, the portion of the disc part extending across the portion of the gate electrode in a second horizontal direction; etching regions of the semiconductor structure exposed by the mask such that the masked portion of the disc part remains to form a channel structure extending across the portion of the gate electrode; and forming a superconductor source contact and a superconductor drain contact on the channel structure at opposite sides of the portion of the gate electrode.

公开(公告)号：US10768138B2

公开(公告)日：2020-09-08

申请号：US16228092

申请日：2018-12-20

Applicant: IMEC VZW

Inventor： Koen Martens ,  Nadine Collaert ,  Eddy Kunnen ,  Simone Severi

IPC: G01N27/414

Abstract: Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.

公开(公告)号：US20190195827A1

公开(公告)日：2019-06-27

申请号：US16228092

申请日：2018-12-20

Applicant: IMEC VZW

Inventor： Koen Martens ,  Nadine Collaert ,  Eddy Kunnen ,  Simone Severi

IPC: G01N27/414

CPC classification number: G01N27/4146 ,  G01N27/4145

Abstract: Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.

公开(公告)号：US20180068898A1

公开(公告)日：2018-03-08

申请号：US15685137

申请日：2017-08-24

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L23/535

CPC classification number: H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

公开(公告)号：US20200328108A1

公开(公告)日：2020-10-15

申请号：US16844845

申请日：2020-04-09

Applicant: IMEC vzw

Inventor： Amey Mahadev Walke ,  Niamh Waldron ,  Nadine Collaert ,  Ming Zhao

IPC: H01L21/762 ,  H01L29/778 ,  H01L29/66 ,  H01L25/16

Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.

公开(公告)号：US20190214474A1

公开(公告)日：2019-07-11

申请号：US16222911

申请日：2018-12-17

Applicant: IMEC vzw

Inventor： Clement Merckling ,  Nadine Collaert

IPC: H01L29/43 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  G06N10/00

CPC classification number: H01L29/437 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02603 ,  H01L21/28264 ,  H01L21/28575 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/32058 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/413 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology is directed to a method of forming a qubit device. In one aspect, the method comprises: forming a gate electrode embedded in an insulating layer formed on a substrate, wherein an upper surface of the substrate is formed from a group IV semiconductor material and the gate electrode extends along the substrate in a first horizontal direction; forming an aperture in the insulating layer, the aperture exposing a portion of the substrate; forming, in an epitaxial growth process, a semiconductor structure comprising a group III-V semiconductor substrate contact part and a group III-V semiconductor disc part, the substrate contact part having a bottom portion abutting the portion of the substrate and an upper portion protruding from the aperture above an upper surface of the insulating layer, the semiconductor disc part extending from the upper portion of the substrate contact part, horizontally along the upper surface of the insulating layer to overlap a portion of the gate electrode; forming a mask covering a portion of the disc part, the portion of the disc part extending across the portion of the gate electrode in a second horizontal direction; etching regions of the semiconductor structure exposed by the mask such that the masked portion of the disc part remains to form a channel structure extending across the portion of the gate electrode; and forming a superconductor source contact and a superconductor drain contact on the channel structure at opposite sides of the portion of the gate electrode.

公开(公告)号：US10309925B2

公开(公告)日：2019-06-04

申请号：US15143262

申请日：2016-04-29

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Voon Yew Thean

IPC: G01N27/414 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices such as field-effect transistor devices configured for biomolecule sensing. In one aspect, a semiconductor chip comprises at least one field-effect transistor device which comprises a source, a drain, a gate stack and a channel region formed between the source and the drain. The gate stack only partially overlaps the channel region at the source side and/or at the drain side, such that a non-overlapped channel region at the source side and/or at the drain side is formed, where the non-overlapped channel region is configured for sensing biomolecules.

公开(公告)号：US10163714B2

公开(公告)日：2018-12-25

申请号：US15685137

申请日：2017-08-24

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L23/535 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L27/02

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

公开(公告)号：US09419110B2

公开(公告)日：2016-08-16

申请号：US14938169

申请日：2015-11-11

Applicant: IMEC VZW

Inventor： Clement Merckling ,  Nadine Collaert

IPC: H01L21/20 ,  H01L29/66 ,  H01L29/20 ,  H01L29/417 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02455 ,  H01L21/02513 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/02661 ,  H01L21/76224 ,  H01L29/20 ,  H01L29/41725 ,  H01L29/7848

Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.

Abstract translation: 提供了一种在SinGe1-n衬底上生长III-V半导体结构的方法，其中n为0至1。 该方法包括以下步骤：（a）使SinGe1-n衬底达到高温; （b）将载体气体中的V族前体暴露于5〜30分钟，由此在该区域形成掺杂区域; （c）使SinGe1-n基板处于低温; （d）将载体气体中的掺杂区域暴露于III族前体，并在载气中暴露于V族前体，直至在成核层上形成5〜15nm的III-V材料的成核层; （e）使SinGe1-n基板达到中间温度; 和（f）将成核层暴露于载气中的III族前体和载气中的V族前体。

公开(公告)号：US20190273115A1

公开(公告)日：2019-09-05

申请号：US16419576

申请日：2019-05-22

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Anne Vandooren ,  Nadine Collaert

IPC: H01L27/148 ,  H01L27/06 ,  H01L21/768 ,  H01L29/417 ,  H01L31/0216 ,  H01L21/822

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.