公开(公告)号：US20230010039A1

公开(公告)日：2023-01-12

申请号：US17859294

申请日：2022-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Martin Heilmann ,  Ming Zhao ,  Nadine Collaert ,  Bertrand Parvais ,  Sachin Yadav

IPC: H01L21/8258 ,  H01L27/06 ,  H01L21/02 ,  C30B29/06 ,  C30B25/18 ,  C30B29/40 ,  C23C16/30 ,  C23C16/02

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes a III-V semiconductor device in a first region of a base substrate and a further device in a second region of the base substrate. The method includes: (a) obtaining a base substrate comprising the first region and the second region, different from the first region; (b) providing a buffer layer over a surface of the base substrate at least in the first region, wherein the buffer layer comprises at least one monolayer of a first two-dimensional layered crystal material; (c) forming, over the buffer layer in the first region, and not in the second region, a III-V semiconductor material; and (d) forming, in the second region, at least part of the further device. A semiconductor structure is also provided.

公开(公告)号：US20220020587A1

公开(公告)日：2022-01-20

申请号：US17375222

申请日：2021-07-14

Applicant: IMEC VZW

Inventor： Ming Zhao ,  Annelies Delabie

IPC: H01L21/02 ,  H01L21/308

Abstract: A method for manufacturing a semiconductor structure that comprises providing a monocrystalline silicon base layer comprising a first region for manufacturing the III-N semiconductor device and a second region for manufacturing the silicon semiconductor device; providing on the monocrystalline silicon base layer a mask layer, the mask layer being interrupted, in the first region, by a recess in the monocrystalline silicon base layer, wherein the mask layer comprises a 2D material; forming, selectively, a layer of gamma-Al2O3 at the bottom of the recess by a first growth process; forming, selectively on the layer of gamma-Al2O3, a III-N semiconductor device stack by a second growth process, and thereafter; manufacturing, in the second region, at least partially a silicon semiconductor device.

公开(公告)号：US20190362967A1

公开(公告)日：2019-11-28

申请号：US16423274

申请日：2019-05-28

Applicant: IMEC VZW

Inventor： Ming Zhao ,  Weiming Guo

IPC: H01L21/02 ,  H01L29/15 ,  H01L29/20 ,  H01L29/06 ,  H01L29/778 ,  H01L21/76 ,  H01L29/66

Abstract: According to an aspect of the present disclosure, there is provided a III-N semiconductor structure comprising: a semiconductor-on-insulator substrate; a buffer structure comprising a superlattice including at least a first superlattice block and a second superlattice block formed on the first superlattice block, the first superlattice block including a repetitive sequence of first superlattice units, each first superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, the second superlattice block including a repetitive sequence of second superlattice units, each second superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, wherein an average aluminum content of the second superlattice block is greater than an average aluminum content of the first superlattice block; and a III-N semiconductor channel layer arranged on the buffer structure.

公开(公告)号：US20200328108A1

公开(公告)日：2020-10-15

申请号：US16844845

申请日：2020-04-09

Applicant: IMEC vzw

Inventor： Amey Mahadev Walke ,  Niamh Waldron ,  Nadine Collaert ,  Ming Zhao

IPC: H01L21/762 ,  H01L29/778 ,  H01L29/66 ,  H01L25/16

Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.

公开(公告)号：US20190157081A1

公开(公告)日：2019-05-23

申请号：US16194904

申请日：2018-11-19

Applicant: IMEC VZW

Inventor： Ming Zhao

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/778

Abstract: A method of forming a semiconductor structure for a III-N semiconductor channel device and a device produced by the method are disclosed. The method includes: (i) forming a buffer structure on a Si-substrate, wherein forming the buffer structure includes: forming a superlattice including at least one superlattice block, each superlattice block including a repetitive sequence of superlattice units, each superlattice unit including a first layer and a second layer formed on the first layer, wherein the first layer is a carbon-doped AlxGa1-xN layer and the second layer is a carbon-doped AlyGa1-yN layer, wherein x and y differ from each other and 0≤x≤1, 0≤y≤1, and wherein said at least first and second layers are epitaxially grown at a temperature of 980° C. or lower, and (ii) forming a III-N semiconductor channel layer above the buffer structure wherein the channel layer is epitaxially grown at a temperature of 1040° C. or lower and is grown to a thickness of 1 μm or smaller.

公开(公告)号：US10192959B2

公开(公告)日：2019-01-29

申请号：US15817343

申请日：2017-11-20

Applicant: IMEC VZW

Inventor： Ming Zhao

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L21/02

Abstract: The present disclosure relates to a III-N based substrate for power electronic devices, comprising a base substrate, a III-N laminate above the base substrate and a buffer layer structure between the base substrate and the III-N laminate. The buffer layer structure comprises at least a first superlattice laminate and a second superlattice laminate above the first superlattice laminate. The first superlattice laminate comprises a repetition of a first superlattice unit which consists of a plurality of first AlGaN layers. The second superlattice laminate comprises a repetition of a second superlattice unit which consists of a plurality of second AlGaN layers. An average aluminum content of the first superlattice laminate is a predetermined difference greater than an average aluminum content of the second superlattice laminate, to improve the vertical breakdown voltage. The present disclosure also relates to a method for manufacturing a III-N based substrate for power electronic devices.

公开(公告)号：US20230395376A1

公开(公告)日：2023-12-07

申请号：US18324752

申请日：2023-05-26

Applicant: IMEC vzw

Inventor： Bertrand Parvais ,  Sachin Yadav ,  Ming Zhao ,  Pieter Cardinael

IPC: H01L21/02 ,  H01L21/322 ,  H01L29/20

CPC classification number: H01L21/0254 ,  H01L21/02181 ,  H01L21/3223 ,  H01L29/2003 ,  H01L21/02381 ,  H01L21/02164 ,  H01L21/0245 ,  H01L21/02532

Abstract: In one aspect, a substrate includes a base substrate, a dielectric layer directly on the base substrate, a trap-rich layer directly on the dielectric layer, and a crystalline semiconductor layer directly on the trap-rich layer. The dielectric layer may be a stack of multiple dielectric sublayers formed of the same dielectric material or formed of two or more different dielectric materials. The substrate can be suitable to epitaxially grow on the surface of the crystalline semiconductor layer one or more layers of a compound semiconductor. One application is the growth of a stack of layers of III-V material with one or more upper layers of the stack being suitable to process in and/or on the layers a number of semiconductor devices such as transistors or diodes. The position of the trap-rich layer, between the dielectric layer and the crystalline semiconductor layer, can enable the neutralization of a parasitic surface conductive (PSC) layer at the interface between the crystalline layer and the compound layer or layers, and of an additional PSC layer caused by a direct contact between the crystalline layer and the dielectric layer. The disclosed technology is equally related to methods of producing the substrate of the disclosed technology.

公开(公告)号：US10991577B2

公开(公告)日：2021-04-27

申请号：US16194904

申请日：2018-11-19

Applicant: IMEC VZW

Inventor： Ming Zhao

IPC: H01L29/06 ,  H01L31/072 ,  H01L29/12 ,  H01L31/0336 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778

Abstract: A method of forming a semiconductor structure for a III-N semiconductor channel device and a device produced by the method are disclosed. The method includes: (i) forming a buffer structure on a Si-substrate, wherein forming the buffer structure includes: forming a superlattice including at least one superlattice block, each superlattice block including a repetitive sequence of superlattice units, each superlattice unit including a first layer and a second layer formed on the first layer, wherein the first layer is a carbon-doped AlxGa1-xN layer and the second layer is a carbon-doped AlyGa1-yN layer, wherein x and y differ from each other and 0≤x≤1, 0≤y≤1, and wherein said at least first and second layers are epitaxially grown at a temperature of 980° C. or lower, and (ii) forming a III-N semiconductor channel layer above the buffer structure wherein the channel layer is epitaxially grown at a temperature of 1040° C. or lower and is grown to a thickness of 1 μm or smaller.

公开(公告)号：US09923050B2

公开(公告)日：2018-03-20

申请号：US15023553

申请日：2014-09-11

Applicant: Siltronic AG ,  IMEC VZW

Inventor： Sarad Bahadur Thapa ,  Ming Zhao ,  Peter Storck ,  Norbert Werner

IPC: H01L29/04 ,  C30B25/18 ,  C30B29/40 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/045 ,  C30B25/18 ,  C30B25/183 ,  C30B29/403 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/205

Abstract: A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the -direction toward the -direction by an angle θ of not less than 0.3° and not more than 6°, the azimuthal tolerance of the inclination being ±0.1°; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlxGa1-xN layers, wherein 0

公开(公告)号：US11476119B2

公开(公告)日：2022-10-18

申请号：US17375222

申请日：2021-07-14

Applicant: IMEC VZW

Inventor： Ming Zhao ,  Annelies Delabie

IPC: H01L21/02 ,  H01L21/308

Abstract: A method for manufacturing a semiconductor structure that comprises providing a monocrystalline silicon base layer comprising a first region for manufacturing the III-N semiconductor device and a second region for manufacturing the silicon semiconductor device; providing on the monocrystalline silicon base layer a mask layer, the mask layer being interrupted, in the first region, by a recess in the monocrystalline silicon base layer, wherein the mask layer comprises a 2D material; forming, selectively, a layer of gamma-Al2O3 at the bottom of the recess by a first growth process; forming, selectively on the layer of gamma-Al2O3, a III-N semiconductor device stack by a second growth process, and thereafter; manufacturing, in the second region, at least partially a silicon semiconductor device.