公开(公告)号：US09417946B2

公开(公告)日：2016-08-16

申请号：US14337699

申请日：2014-07-22

Applicant: Infineon Technologies AG

Inventor： Antonio Vilela ,  Andre Roger

IPC: G06F11/07 ,  G06F11/16

CPC classification number: G06F11/0763 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/1695

Abstract: Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

Abstract translation: 实施例涉及用于系统中的错误容纳的系统和方法，包括通过多个处理单元处理输入信号来检测错误，以及延迟处理单元的至少一个输出信号，以在检测到错误的情况下使得在 处理单元的至少一个输出信号将导致错误传播通过系统。

公开(公告)号：US09218236B2

公开(公告)日：2015-12-22

申请号：US13662846

申请日：2012-10-29

Applicant: Infineon Technologies AG

Inventor： Antonio Vilela ,  Andre Roger

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0739 ,  G06F11/0757

Abstract: An error signal handling unit includes an error handler configured to receive an error signal indicating an error condition. The error handler is further configured to receive a recovery signal indicating a mitigation of the error condition or indicating that a mitigation of the error condition is possible. Furthermore, the error handler is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the error handler does not receive the recovery signal, and otherwise omit outputting the error condition signal.

Abstract translation: 错误信号处理单元包括错误处理器，该错误处理器被配置为接收指示错误状况的错误信号。 错误处理器还被配置为接收指示减轻错误状况的恢复信号或指示可以减轻错误状况。 此外，错误处理器还被配置为响应于错误信号的接收而输出基于误差信号的错误状态信号，如果在从接收到错误信号的给定延迟时间内，错误处理程序没有接收到恢复 信号，否则省略输出错误状态信号。

公开(公告)号：US08799703B2

公开(公告)日：2014-08-05

申请号：US14027464

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Simon Brewerton ,  Patrick Leteinturier ,  Oreste Bernardi ,  Antonio Vilela ,  Klaus Scheibert ,  Jens Barrenscheen

IPC: G06F11/00

CPC classification number: G06F11/263 ,  G06F11/0739 ,  G06F11/0754 ,  G06F11/3013 ,  G06F11/3068

Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract translation: 本发明的一些实施例涉及一种嵌入式处理系统。 该系统包括用于存储多个操作指令的存储器单元和耦合到存储器单元的处理单元。 处理单元可以执行与各个操作指令相对应的逻辑操作。 输入/输出（I / O）接口接收第一时变波形并提供基于第一时变波形的I / O信号。 比较单元，耦合到所述处理单元，并且适于基于所述I / O信号是否与参考信号具有预定关系来选择性地确定错误信号，其中所述预定关系在正常操作期间成立，但是当意外 事件发生并导致至少一个I / O信号和参考信号的意外变化。

公开(公告)号：US09950710B2

公开(公告)日：2018-04-24

申请号：US15041789

申请日：2016-02-11

Applicant: Infineon Technologies AG

Inventor： Axel Freiwald ,  Bejoy Mathews ,  Antonio Vilela

IPC: B60W50/029 ,  G05B9/03 ,  B60R16/023

Abstract: A device for operating an apparatus comprising a first controller configured to be controlled by a first control signal, a second controller configured to be controlled by a second control signal, a control unit operatively connected to the first controller and the second controller, wherein the first controller and the second controller are both configured to operate the apparatus.

公开(公告)号：US20170302441A1

公开(公告)日：2017-10-19

申请号：US15486367

申请日：2017-04-13

Applicant: Infineon Technologies AG

Inventor： Christopher Temple ,  Simon Cottam ,  Frank Hellwig ,  Antonio Vilela

IPC: H04L9/06 ,  G06F21/64 ,  G06F21/85 ,  H04L9/00

CPC classification number: H04L9/0643 ,  G06F21/64 ,  G06F21/79 ,  G06F21/85 ,  H04L9/004 ,  H04L2209/127 ,  H04L2209/84

Abstract: According to various embodiments, a control device is described including an application core including a processor, a memory and a direct memory access controller and a security module coupled to the application core via a computer bus. The direct memory access controller is configured to read data from the memory, generate a hash value for the data and provide the hash value to the security module via the computer bus. The security module is configured to process the hash value.

公开(公告)号：US20160264150A1

公开(公告)日：2016-09-15

申请号：US15041789

申请日：2016-02-11

Applicant: Infineon Technologies AG

Inventor： Axel Freiwald ,  Bejoy Mathews ,  Antonio Vilela

IPC: B60W50/029 ,  B60R16/023 ,  G05B9/03

CPC classification number: B60W50/029 ,  B60W50/023 ,  B60W2050/0018 ,  B60W2050/0292 ,  G05B9/03

Abstract: A device for operating an apparatus comprising a first controller configured to be controlled by a first control signal, a second controller configured to be controlled by a second control signal, a control unit operatively connected to the first controller and the second controller, wherein the first controller and the second controller are both configured to operate the apparatus.

Abstract translation: 一种用于操作装置的装置，包括被配置为由第一控制信号控制的第一控制器，被配置为由第二控制信号控制的第二控制器，可操作地连接到第一控制器和第二控制器的控制单元， 控制器和第二控制器都被配置为操作设备。

公开(公告)号：US09128838B2

公开(公告)日：2015-09-08

申请号：US13957851

申请日：2013-08-02

Applicant: Infineon Technologies AG

Inventor： Antonio Vilela ,  Simon Cottam

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/16 ,  G06F11/22 ,  G06F11/277

CPC classification number: G06F11/0772 ,  G06F11/16 ,  G06F11/1637 ,  G06F11/1654 ,  G06F11/167 ,  G06F11/1675 ,  G06F11/2221 ,  G06F11/277 ,  G06F2201/845

Abstract: A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other.

Abstract translation: 用于直接存储器访问（DMA）操作的系统和方法提供接收DMA请求者，将接收的DMA请求者分配给多个DMA引擎中的一个或多个以用于处理所接收的DMA请求者，并且如果所接收的DMA请求者之一是 将所述安全请求者分配给所述多个DMA引擎中的至少两个DMA引擎以处理所述安全请求者，禁用用于将所述至少两个DMA引擎的至少一个DMA引擎耦合到存储器的总线接口，将所述至少两个DMA引擎的输出进行比较 所述至少两个DMA引擎，并且如果所述至少两个DMA引擎的输出的比较彼此不同，则产生错误消息。

公开(公告)号：US20140122942A1

公开(公告)日：2014-05-01

申请号：US13662846

申请日：2012-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Antonio Vilela ,  Andre Roger

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0739 ,  G06F11/0757

Abstract: An error signal handling unit includes an error handler configured to receive an error signal indicating an error condition. The error handler is further configured to receive a recovery signal indicating a mitigation of the error condition or indicating that a mitigation of the error condition is possible. Furthermore, the error handler is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the error handler does not receive the recovery signal, and otherwise omit outputting the error condition signal.

Abstract translation: 错误信号处理单元包括错误处理器，该错误处理器被配置为接收指示错误状况的错误信号。 错误处理器还被配置为接收指示减轻错误状况的恢复信号或指示可以减轻错误状况。 此外，错误处理器还被配置为响应于错误信号的接收而输出基于误差信号的错误状态信号，如果在从接收到错误信号的给定延迟时间内，错误处理程序没有接收到恢复 信号，否则省略输出错误状态信号。