公开(公告)号：US20230239368A1

公开(公告)日：2023-07-27

申请号：US18130733

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Daniel Daly ,  John Fastabend ,  Matthew Vick ,  Brian J. Skerry ,  Marco Varlese ,  Jing Mark Chen ,  Danny Y. Zhou

IPC: H04L67/561 ,  H04L69/22 ,  H04L69/324 ,  H04L49/00

CPC classification number: H04L67/561 ,  H04L69/22 ,  H04L69/324 ,  H04L49/70

Abstract: Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.

公开(公告)号：US10853277B2

公开(公告)日：2020-12-01

申请号：US15573114

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Cunming Liang ,  Danny Y. Zhou ,  David E. Cohen ,  James R. Harris

IPC: G06F13/16 ,  G06F3/00 ,  G06F9/50 ,  G06F13/28 ,  G06F13/42 ,  G06F9/455

Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include logic to identify a Process Address Space Identifier (PASID) for a process or container of the host device and logic to associate the PASID with an individual queue pair of a hardware device of the host device, wherein the queue pair includes two complementary queues and wherein the queue pair is owned by the process or container upon association with the PASID. Other embodiments may be disclosed and/or claimed.