公开(公告)号：US12170624B2

公开(公告)日：2024-12-17

申请号：US17492420

申请日：2021-10-01

Applicant: Intel Corporation

Inventor： Anjali Singhai Jain ,  Daniel Daly ,  Sridhar Samudrala ,  Linden Cornett ,  Phani Burra ,  Brett Creeley

IPC: H04L47/762 ,  H04L9/40 ,  H04L47/2425 ,  H04L47/78 ,  H04L47/80

Abstract: Examples described herein relate to one or more processors, when operational, to execute instructions stored in memory device, to cause performance of: execute a driver that is to: negotiate capabilities of hardware with a control plane for a virtualized execution environment and limit capabilities of the hardware available to the virtualized execution environment based on a service level agreement (SLA) associated with the virtualized execution environment. In some examples, the driver is to advertise hardware capabilities requested by the virtualized execution environment. In some examples, the control plane is to set capabilities of a hardware available to the virtualized execution environment based on the SLA.

公开(公告)号：US20190327323A1

公开(公告)日：2019-10-24

申请号：US16460798

申请日：2019-07-02

Applicant: Intel Corporation

Inventor： Daniel Daly ,  John Fastabend ,  Matthew Vick ,  Brian J. Skerry ,  Marco Varlese ,  Jing Mark Chen ,  Danny Y. Zhou

IPC: H04L29/08 ,  H04L12/931 ,  H04L29/06

Abstract: Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.

公开(公告)号：US09912774B2

公开(公告)日：2018-03-06

申请号：US14977810

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Daniel Daly ,  John Fastabend ,  Matthew Vick ,  Brian J. Skerry ,  Marco Varlese ,  Jing Mark Chen ,  Danny Y. Zhou

IPC: H04L12/28 ,  H04L29/08 ,  H04L29/06 ,  H04L12/931

CPC classification number: H04L67/2804 ,  H04L49/70 ,  H04L69/22 ,  H04L69/324

Abstract: Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.

公开(公告)号：US11936571B2

公开(公告)日：2024-03-19

申请号：US17981255

申请日：2022-11-04

Applicant: Intel Corporation

Inventor： Shaopeng He ,  Cunming Liang ,  Jiang Yu ,  Ziye Yang ,  Ping Yu ,  Bo Cui ,  Jingjing Wu ,  Liang Ma ,  Hongjun Ni ,  Zhiguo Wen ,  Changpeng Liu ,  Anjali Singhai Jain ,  Daniel Daly ,  Yadong Li

IPC: H04L49/9057 ,  H04L1/1829 ,  H04L47/34 ,  H04L47/56 ,  H04L49/552 ,  H04L49/90

CPC classification number: H04L49/9057 ,  H04L1/1841 ,  H04L47/34 ,  H04L47/56 ,  H04L49/552 ,  H04L49/9094

Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.

公开(公告)号：US11677851B2

公开(公告)日：2023-06-13

申请号：US17484004

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Daniel Daly ,  John Fastabend ,  Matthew Vick ,  Brian J. Skerry ,  Marco Varlese ,  Jing Mark Chen ,  Danny Y. Zhou

IPC: H04L67/561 ,  H04L69/22 ,  H04L69/324 ,  H04L49/00

CPC classification number: H04L67/561 ,  H04L49/70 ,  H04L69/22 ,  H04L69/324

Abstract: Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.

公开(公告)号：US20220060555A1

公开(公告)日：2022-02-24

申请号：US17484004

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Daniel Daly ,  John Fastabend ,  Matthew Vick ,  Brian J. Skerry ,  Marco Varlese ,  Jing Mark Chen ,  Danny Y. Zhou

IPC: H04L29/08 ,  H04L29/06 ,  H04L12/931

Abstract: Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.

公开(公告)号：US20180234516A1

公开(公告)日：2018-08-16

申请号：US15878966

申请日：2018-01-24

Applicant: Intel Corporation

Inventor： Daniel Daly ,  John R. Fastabend ,  Matthew Vick ,  Brian J. Skerry ,  Marco Varlese ,  Jing Mark Chen ,  Danny Y. Zhou

IPC: H04L29/08 ,  H04L12/931 ,  H04L29/06

CPC classification number: H04L67/2804 ,  H04L49/70 ,  H04L69/22 ,  H04L69/324

Abstract: Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.

公开(公告)号：US09742616B2

公开(公告)日：2017-08-22

申请号：US14580766

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Nrupal Jani ,  Ilango Ganga ,  Daniel Daly ,  John Fastabend ,  Neerav Parikh ,  Elizabeth Kappler ,  Brian J. Skerry ,  Calin Gherghe ,  Sanjeev Jain ,  Ben-Zion Friedman

IPC: H04L29/06 ,  H04L12/54 ,  H04L12/931 ,  G06F9/455

CPC classification number: H04L29/0653 ,  G06F9/45558 ,  G06F2009/45595 ,  H04L12/56 ,  H04L49/70 ,  H04L69/22

Abstract: Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.

公开(公告)号：US12212600B2

公开(公告)日：2025-01-28

申请号：US17189219

申请日：2021-03-01

Applicant: Intel Corporation

Inventor： Helia A. Naeimi ,  Sivakumar Munnangi ,  Namrata Limaye ,  Arvind Srinivasan ,  Gargi Saha ,  Hung Nguyen ,  Daniel Daly

IPC: H04L29/06 ,  H04L9/40

Abstract: Examples described herein relate to a Transport Layer Security (TLS) offload engine to: based on detection of encrypted data unassociated with a previously detected data header: search for one or more data headers; identify at least two candidate data headers for validation; and based on receipt of an indication that the at least two candidate data headers are valid, perform decryption of received data in one or more packets. In some examples, the TLS offload engine is to: based on receipt of an indication that one or more of the at least two candidate data headers is not a valid header, search for two or more other candidate data headers.

公开(公告)号：US12192236B2

公开(公告)日：2025-01-07

申请号：US16838888

申请日：2020-04-02

Applicant: Intel Corporation

Inventor： Arvind Srinivasan ,  Daniel Daly

IPC: H04L9/40 ,  H04L5/00 ,  H04L69/166

Abstract: Examples described herein relate to an interface that is to receive data for transmission and based on indication of failure of receipt of one or more packets that carry segments of the data, cause re-transmission of solely one or more of the multiple packets that comprise a segment of the data referenced by the indication of failure of receipt of one or more packets. In some examples, the interface is to encrypt the data using an encryption engine and to segment the data for transmission using one or more packets. In some examples, the interface is to receive the data and an indication of which segment of the data to re-transmit; encrypt the data; segment the encrypted data into one or more packets; and based on the indication of which segment of the data to re-transmit, transmit solely one or more of the multiple packets that comprise a segment of the data referenced by the indication of failure of receipt of one or more packets.