公开(公告)号：US10915356B2

公开(公告)日：2021-02-09

申请号：US16117091

申请日：2018-08-30

Applicant: Intel Corporation

Inventor： Ramakrishnan Sivakumar ,  Vijay Dhanraj ,  Russell Fenger ,  Guy Therien

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.

公开(公告)号：US10175740B2

公开(公告)日：2019-01-08

申请号：US15135682

申请日：2016-04-22

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Paul Diefenbaugh ,  Guy Therien ,  Nir Rosenzweig

IPC: G06F1/32

Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.

公开(公告)号：US20160259392A1

公开(公告)日：2016-09-08

申请号：US15135682

申请日：2016-04-22

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Paul Diefenbaugh ,  Guy Therien ,  Nir Rosenzweig

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3243 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152

Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元（PCU），以控制处理器的功率消耗。 PCU可以包括映射逻辑以从操作系统（OS）接收性能标度值，并且至少部分地基于性能标度值来计算动态性能 - 频率映射。 描述和要求保护其他实施例。

公开(公告)号：US08874947B2

公开(公告)日：2014-10-28

申请号：US13893846

申请日：2013-05-14

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Barnes Cooper ,  Guy Therien ,  Eliezer Weissmann ,  Anil Aggarwal

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.

Abstract translation: 提出了处理平台和处理平台中央处理单元功耗控制方法。 通过操作该方法，处理平台能够设置较高的性能状态限制和较低的性能状态限制。 较高的性能状态限制基于中央处理单元活动速率值，较低的性能状态限制基于操作系统执行操作系统任务的最低要求。 性能状态值根据电源管理策略在下限和上限的范围内变化。