公开(公告)号：US11521943B2

公开(公告)日：2022-12-06

申请号：US17229316

申请日：2021-04-13

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Tin Poay Chuah ,  Chin Lee Kuan

IPC: H05K1/18 ,  H01L23/64 ,  H01L23/498 ,  H05K1/02 ,  H01L23/50 ,  H01L23/13

Abstract: A capacitor loop substrate assembly includes a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects are formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

公开(公告)号：US11521932B2

公开(公告)日：2022-12-06

申请号：US17025990

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Ping Ping Ooi ,  Seok Ling Lim

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

公开(公告)号：US11508660B2

公开(公告)日：2022-11-22

申请号：US17089745

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/50

Abstract: A semiconductor package including a molded power delivery module arranged between a package substrate and a semiconductor chip and including a plurality of input conductive structures and a plurality of reference conductive structures, wherein the input conductive structures alternate between the plurality of reference conductive structures, wherein the input conductive structure is electrically coupled with a chip input voltage terminal and a package input voltage terminal, wherein each of the plurality of reference conductive structures are electrically coupled with a semiconductor chip reference terminal and a package reference terminal.

公开(公告)号：US20220068836A1

公开(公告)日：2022-03-03

申请号：US17522603

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/552 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.

公开(公告)号：US11195801B2

公开(公告)日：2021-12-07

申请号：US16663853

申请日：2019-10-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/552 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.

公开(公告)号：US20210183776A1

公开(公告)日：2021-06-17

申请号：US17025990

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Ping Ping Ooi ,  Seok Ling Lim

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

公开(公告)号：US10985147B2

公开(公告)日：2021-04-20

申请号：US16017719

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Chin Lee Kuan

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538 ,  H01L23/498

Abstract: A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.

公开(公告)号：US20200168528A1

公开(公告)日：2020-05-28

申请号：US16663001

申请日：2019-10-24

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L21/768 ,  H01L25/00

Abstract: Disclosed embodiments include a multi-chip package that includes an embedded reference plane between two stacked semiconductive devices, with through-silicon vias that penetrate the reference plane, including reference-voltage vias that contact the reference plane, and signal and power-delivery vias that are insulated from the reference plane. A third semiconductive device is seated with active devices and metallization on the second conductive device.

公开(公告)号：US20200006253A1

公开(公告)日：2020-01-02

申请号：US16419683

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

IPC: H01L23/00 ,  H01L23/522

Abstract: To maintain the integrity of electrical contacts at a build-up layer of a chip package, while reducing electrical interference caused by a chip connected to the build-up layer, the chip package can include a stiffener formed from an electrically conductive material and positioned between the chip and the build-up layer. The chip can electrically connect to the build-up layer through electrical connections that extend through the stiffener. Compared with a stiffener that extends only over a single chip of the chip package, the present stiffener can help prevent warpage or other mechanical deformities that can degrade electrical contacts away from the chip at the build-up layer. Compared with a stiffener that extends only over an area away from the chip, such as a peripheral area, the present stiffener can help reduce electrical interference in an area of the build-up layer near the chip.

公开(公告)号：US12183722B2

公开(公告)日：2024-12-31

申请号：US17638039

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L49/02

Abstract: Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.