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    WEIGHT-SHIFTING MECHANISM FOR CONVOLUTIONAL NEURAL NETWORKS
    11.
    发明申请
    WEIGHT-SHIFTING MECHANISM FOR CONVOLUTIONAL NEURAL NETWORKS 审中-公开
    用于交互式神经网络的重量分配机制

    公开(公告)号：US20160026912A1

    公开(公告)日：2016-01-28

    申请号：US14337979

    申请日：2014-07-22

    Applicant: Intel Corporation

    Inventor： Ayose J. Falcon ,  Marc Lupon ,  Enric Herrero Abellanas ,  Pedro Lopez ,  Fernando Latorre ,  Frederico C. Pratas ,  Georgios Tournavitis

    IPC: G06N3/06 ,  G06N3/08

    CPC classification number: G06N3/06 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08

    Abstract: A processor includes a processor core and a calculation circuit. The processor core includes logic determine a set of weights for use in a convolutional neural network (CNN) calculation and scale up the weights using a scale value. The calculation circuit includes logic to receive the scale value, the set of weights, and a set of input values, wherein each input value and associated weight of a same fixed size. The calculation circuit also includes logic to determine results from convolutional neural network (CNN) calculations based upon the set of weights applied to the set of input values, scale down the results using the scale value, truncate the scaled down results to the fixed size, and communicatively couple the truncated results to an output for a layer of the CNN.

    Abstract translation: 处理器包括处理器核心和计算电路。 处理器核心包括确定用于卷积神经网络（CNN）计算的一组权重的逻辑，并使用比例值来放大权重。 计算电路包括接收比例值，权重集合和一组输入值的逻辑，其中每个输入值和相同固定大小的相关权重。 计算电路还包括基于应用于输入值集合的权重集合来确定卷积神经网络（CNN）计算结果的逻辑，使用比例值缩小结果，将缩小的结果截断为固定大小， 并将截断的结果通信地耦合到CNN的层的输出。

    Double rounded combined floating-point multiply and add
    15.
    发明授权
    Double rounded combined floating-point multiply and add 有权

    公开(公告)号：US09477441B2

    公开(公告)日：2016-10-25

    申请号：US14948943

    申请日：2015-11-23

    Applicant: Intel Corporation

    Inventor： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

    IPC: G06F7/38 ,  G06F7/487 ,  G06F7/483 ,  G06F7/544 ,  G06F7/485 ,  G06F7/499

    CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

    Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

    INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION
    16.
    发明申请
    INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION 审中-公开
    大容量存储器重新引导的指令和逻辑

    公开(公告)号：US20160092222A1

    公开(公告)日：2016-03-31

    申请号：US14496113

    申请日：2014-09-25

    Applicant: Intel Corporation

    Inventor： David Pardo Keppel ,  Denis M. Khartikov ,  Fernando LaTorre ,  Marc Lupon ,  Grigorios Magklis ,  Naveen Neelakantam ,  Georgios Tournavitis ,  Polychronis Xekalakis

    IPC: G06F9/30

    CPC classification number: G06F9/30185 ,  G06F9/384 ,  G06F9/3857

    Abstract: A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.

    Abstract translation: 处理器包括前端，解码器，分配器和退休单元。 解码器包括用于识别终点范围（EOLR）指示符的逻辑。 EOLR指示符指定体系结构寄存器和不使用体系结构寄存器的代码中的位置。 分配器包括基于EOLR指示器扫描架构寄存器到物理寄存器的映射的逻辑。 分配器还包括生成用于将体系结构寄存器与物理寄存器取消关联的请求的逻辑。 退休单位包括将架构寄存器与物理寄存器取消关联的逻辑。

    DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD
    17.
    发明申请
    DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD 有权
    双重圆形组合浮点数乘法和加法

    公开(公告)号：US20160077802A1

    公开(公告)日：2016-03-17

    申请号：US14948943

    申请日：2015-11-23

    Applicant: Intel Corporation

    Inventor： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

    IPC: G06F7/487 ,  G06F7/499 ,  G06F7/485

    CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

    Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

    Abstract translation: 公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。 实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。 所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数， 基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。 分别使用溢出检测选择最终结果。

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