公开(公告)号：US20220108039A1

公开(公告)日：2022-04-07

申请号：US17551961

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Rafael Misoczki ,  Santosh Ghosh ,  Raghavan Kumar ,  Manoj Sastry ,  Andrew H. Reinders

IPC: G06F21/72 ,  G06F21/76 ,  H04L9/32 ,  H04L9/08

Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.

公开(公告)号：US20220094518A1

公开(公告)日：2022-03-24

申请号：US17025344

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Rafael Misoczki ,  Rosario Cammarota ,  Manoj Sastry

IPC: H04L9/00 ,  H04L9/30

Abstract: Embodiments are directed to low circuit depth homomorphic encryption evaluations. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, determine two coefficients of the ciphertext for HE evaluation, input the two coefficients as a first operand and a second operand to a pipeline multiplier for low circuit depth HE evaluation, perform combinatorial multiplication between the first operand and portions of the second operand, accumulate results of the combinatorial multiplication at each stage of the pipeline multiplier, and perform reduction with Mersenne prime modulus on a resulting accumulated output of the combinatorial multipliers of the pipeline multiplier.

公开(公告)号：US11218320B2

公开(公告)日：2022-01-04

申请号：US16455908

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L29/06 ,  H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

公开(公告)号：US20210306155A1

公开(公告)日：2021-09-30

申请号：US16830844

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Manoj Sastry ,  Rafael Misoczki ,  Jordan Loney ,  David M. Wheeler

IPC: H04L9/32 ,  G06F21/72

Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.

公开(公告)号：US20210119766A1

公开(公告)日：2021-04-22

申请号：US17133711

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Vikram B. Suresh ,  Rosario Cammarota ,  Sanu K. Mathew ,  Zeshan A. Chishti ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/00 ,  G06F12/0802 ,  G06N20/00

Abstract: Technologies for memory and I/O efficient operations on homomorphically encrypted data are disclosed. In the illustrative embodiment, a cloud compute device is to perform operations on homomorphically encrypted data. In order to reduce memory storage space and network and I/O bandwidth, ciphertext blocks can be manipulated as data structures, allowing operands for operations on a compute engine to be created on the fly as the compute engine is performing other operations, using orders of magnitude less storage space and bandwidth.

公开(公告)号：US20190327096A1

公开(公告)日：2019-10-24

申请号：US16456058

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Xiruo Liu ,  Rafael Misoczki ,  Manoj R. Sastry ,  Santosh Ghosh ,  Li Zhao

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/30 ,  H04L9/14

Abstract: An attestation protocol between a prover device (P), a verifier device (V), and a trusted third-party device (TPP). P and TPP have a first trust relationship represented by a first cryptographic representation based on a one-or-few-times, hash-based, signature key. V sends an attestation request to P, with the attestation request including a second cryptographic representation of a second trust relationship between V and TPP. In response to the attestation request, P sends a validation request to TPP, with the validation request being based on a cryptographic association of the first trust relationship and the second trust relationship. TPP provides a validation response including a cryptographic representation of verification of validity of the first trust relationship and the second trust relationship. P sends an attestation response to V based on the validation response.

公开(公告)号：US20190319796A1

公开(公告)日：2019-10-17

申请号：US16456034

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： SANTOSH GHOSH ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/08 ,  H04L9/30 ,  H04L9/06

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

公开(公告)号：US20170230182A1

公开(公告)日：2017-08-10

申请号：US15083562

申请日：2016-03-29

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Rachid El Bansarkhani

IPC: H04L9/32 ,  H04L9/08 ,  H04W12/04 ,  H04L9/30 ,  H04L29/06 ,  H04W12/06 ,  H04L9/06 ,  H04L9/14

CPC classification number: H04L9/3247 ,  G06F21/44 ,  G06F21/602 ,  H04L9/0836 ,  H04L9/3255 ,  H04L63/065

Abstract: Technologies for remote attestation include a group member device to generate a signature of a message using a cryptographic key assigned to the group member device by a group manager and determine an authentication path that indicates a plurality of cryptographic hashes necessary to compute a group public key of a group associated with a plurality of group member devices. The cryptographic key is assigned to the group member device based on a permutation of a set of cryptographic keys generated by the plurality of group member devices. The group member device transmits the signature and the authentication path to a verifier device for verification of the signature.

公开(公告)号：US20170155514A1

公开(公告)日：2017-06-01

申请号：US14955255

申请日：2015-12-01

Applicant: INTEL CORPORATION

Inventor： Steffen Schulz ,  Rafael Misoczki ,  Manoj R. Sastry ,  Jesse Walker

IPC: H04L9/32 ,  H04L9/30 ,  H04L9/14 ,  G06F9/445 ,  H04L29/06

CPC classification number: H04L9/3247 ,  G06F8/65 ,  H04L9/0891 ,  H04L9/14 ,  H04L9/304 ,  H04L9/3242 ,  H04L63/06 ,  H04L63/123 ,  H04L67/34

Abstract: In a method for validating software updates, a data processing system contains a current version of a software component. The data processing system saves at least first and second current advance keys (AKs). After saving the current AKs, the data processing system receives an update package for a new version of the software component. The data processing system extracts a digital signature and two or more new AKs from the update package. The data processing system uses at least one current AK to determine whether the digital signature is valid. In response to a determination that the digital signature is valid, the data processing system uses a software image from the update package to update the software component, and the data processing system saves the new AKs, for subsequent utilization as the current AKs. Other embodiments are described and claimed.

公开(公告)号：US11770262B2

公开(公告)日：2023-09-26

申请号：US17568919

申请日：2022-01-05

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Vikram Suresh ,  Santosh Ghosh ,  Manoj Sastry ,  Sanu Mathew ,  Raghavan Kumar

IPC: H04L9/08 ,  H04L9/00 ,  H04L9/32

CPC classification number: H04L9/3247 ,  H04L9/085 ,  H04L9/0852 ,  H04L9/50

Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.