公开(公告)号：US10083033B2

公开(公告)日：2018-09-25

申请号：US14643855

申请日：2015-03-10

Applicant: INTEL CORPORATION

Inventor： Sebastian Winkel ,  Girish Venkatasubramanian ,  Tyler N. Sondag ,  Rolf Kassa

IPC: G06F9/30

CPC classification number: G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863

Abstract: A method and apparatus are described for efficient register reclamation. For example, one embodiment of an apparatus comprises: single usage detection and tagging logic to examine a sequence of instructions to detect logical registers used by the sequence of instructions that have a single use and to tag an instruction as a single usage instruction if the instruction is a consumer of a logical register that has a single use; an allocator to allocate processor resources to execute the sequence of instructions, the processor resources including physical registers mapped to logical registers to execute the sequence of instructions; and register reclamation logic to free up a logical to physical mapping of a single use register in response to detecting the tag provided by the instruction tagging logic.

公开(公告)号：US09965320B2

公开(公告)日：2018-05-08

申请号：US14142475

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Rolf Kassa ,  Justin E. Gottschlich ,  Shiliang Hu ,  Gilles A. Pokam ,  Robert C. Knauerhase

IPC: G06F9/46 ,  G06F15/00 ,  G06F9/52 ,  G06F11/07

CPC classification number: G06F9/467 ,  G06F9/528 ,  G06F11/0724 ,  G06F11/0772

Abstract: A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted.

公开(公告)号：US09875108B2

公开(公告)日：2018-01-23

申请号：US13844817

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： Gilles A. Pokam ,  Rolf Kassa ,  Klaus Danne ,  Tim Kranich ,  Cristiano L. Pereira ,  Justin E. Gottschlich ,  Shiliang Hu

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0811 ,  G06F12/0842

CPC classification number: G06F9/3834 ,  G06F9/321 ,  G06F12/0811 ,  G06F12/0842 ,  Y02B70/12 ,  Y02D10/13

Abstract: A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.

公开(公告)号：US09697040B2

公开(公告)日：2017-07-04

申请号：US14226312

申请日：2014-03-26

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu ,  Rolf Kassa ,  Youfeng Wu ,  Irina Calciu

IPC: G06F9/44 ,  G06F9/45 ,  G06F9/46 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F9/467 ,  G06F11/34 ,  G06F11/362 ,  G06F11/3648

Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.

公开(公告)号：US20140281274A1

公开(公告)日：2014-09-18

申请号：US13844817

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： Gilles A. Pokam ,  Rolf Kassa ,  Klaus Danne ,  Tim Kranich ,  Cristiano L. Pereira ,  Justin E. Gottschlich ,  Shiliang Hu

IPC: G06F12/08

CPC classification number: G06F9/3834 ,  G06F9/321 ,  G06F12/0811 ,  G06F12/0842 ,  Y02B70/12 ,  Y02D10/13

Abstract: A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.

Abstract translation: 一种用于在存在复杂多操作指令的情况下记录共享存储器访问的交错的系统，处理器和方法。 公开了对指令原子性（IA）的扩展，使得如果硬件已经记录了由于指令原子性违规（IAV）引起的依赖关系，则软件可以推断关于多操作执行的部分信息。 通过监视多操作指令的进度，不需要复杂的多操作仿真。