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公开(公告)号：US11748103B2
公开(公告)日：2023-09-05
申请号：US17672253
申请日：2022-02-15
Applicant: Intel Corporation
Inventor： Dan Baum , Michael Espig , James Guilford , Wajdi K. Feghali , Raanan Sade , Christopher J. Hughes , Robert Valentine , Bret Toll , Elmoustapha Ould-Ahmed-Vall , Mark J. Charney , Vinodh Gopal , Ronen Zohar , Alexander F. Heinecke
CPC classification number: G06F9/30178 , G06F9/3013 , G06F9/30036 , G06F9/30145 , G06F9/3802
Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.
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12.发明授权公开(公告)号：US11507376B2
公开(公告)日：2022-11-22
申请号：US17152160
申请日：2021-01-19
Applicant: INTEL CORPORATION
Inventor： Bret Toll , Alexander F. Heinecke , Christopher J. Hughes , Ronen Zohar , Michael Espig , Dan Baum , Raanan Sade , Robert Valentine , Mark J. Charney , Elmoustapha Ould-Ahmed-Vall
IPC: G06F17/16 , G06F12/02 , G06F9/30 , G06F12/06 , G06F9/38 , G06T1/20 , G06F3/06 , G06F12/0897 , G06F12/0875 , G06F9/345
Abstract: Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.
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公开(公告)号：US20210216314A1
公开(公告)日：2021-07-15
申请号：US17108083
申请日：2020-12-01
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
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公开(公告)号：US10114641B2
公开(公告)日：2018-10-30
申请号：US15485378
申请日：2017-04-12
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
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公开(公告)号：US10114640B2
公开(公告)日：2018-10-30
申请号：US15485372
申请日：2017-04-12
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20170322803A1
公开(公告)日：2017-11-09
申请号：US15661199
申请日：2017-07-27
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
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公开(公告)号：US20170322802A1
公开(公告)日：2017-11-09
申请号：US15661190
申请日：2017-07-27
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
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公开(公告)号：US20170220349A1
公开(公告)日：2017-08-03
申请号：US15485378
申请日：2017-04-12
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
CPC classification number: G06F9/30014 , G06F7/49947 , G06F9/30025 , G06F9/30036 , G06F9/30167 , G06F9/30181 , G06F9/30185 , G06F17/10
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
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公开(公告)号：US20170220348A1
公开(公告)日：2017-08-03
申请号：US15485372
申请日：2017-04-12
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
CPC classification number: G06F9/30014 , G06F7/49947 , G06F9/30025 , G06F9/30036 , G06F9/30167 , G06F9/30181 , G06F9/30185 , G06F17/10
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
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公开(公告)号：US09037626B2
公开(公告)日：2015-05-19
申请号：US13843236
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark J. Buxton , Zeev Sperber , Koby Gottlieb
CPC classification number: G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
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