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    Packet switching
    11.
    发明授权
    Packet switching 有权

    公开(公告)号：US10447604B2

    公开(公告)日：2019-10-15

    申请号：US15613440

    申请日：2017-06-05

    Applicant: Intel Corporation

    Inventor： Mazhar I. Memon ,  Steven R. King

    IPC: H04L12/851 ,  H04L12/801 ,  H04L12/823 ,  H04L12/933 ,  H04L12/859 ,  H04L12/863

    Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed3 involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

    Packet switching
    13.
    发明授权
    Packet switching 有权
    分组交换

    公开(公告)号：US08934344B2

    公开(公告)日：2015-01-13

    申请号：US14167533

    申请日：2014-01-29

    Applicant: Intel Corporation

    Inventor： Mazhar I. Memon ,  Steven R. King

    IPC: G01R31/06 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26 ,  H04L12/863 ,  H04L12/801 ,  H04L12/851 ,  H04L12/823 ,  H04L12/933 ,  H04L12/859

    CPC classification number: H04L47/24 ,  H04L47/10 ,  H04L47/2433 ,  H04L47/2475 ,  H04L47/2483 ,  H04L47/32 ,  H04L47/50 ,  H04L47/6255 ,  H04L47/627 ,  H04L49/109

    Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

    Abstract translation: 在一个实施例中，提供了一种装置，其可以包括集成电路，其包括开关电路，用于至少部分地确定涉及分组的要执行的动作。 该确定可以至少部分地基于至少部分地从分组确定的流信息和分组处理策略信息。 电路可以检查策略信息以确定是否建立了至少部分地对应于流信息的先前建立的分组处理策略。 如果电路至少部分地确定策略尚未建立并且分组是至少部分地对应于流信息的流中的第一分组，则开关电路可以请求至少一个开关控制程序模块 至少部分地建立至少部分地对应于流信息的新分组处理策略。

    Configurable Reduced Instruction Set Core
    14.
    发明申请
    Configurable Reduced Instruction Set Core 审中-公开
    可配置的减少指令集核心

    公开(公告)号：US20140223145A1

    公开(公告)日：2014-08-07

    申请号：US13992797

    申请日：2011-12-30

    Applicant: INTEL CORPORATION

    Inventor： Srihari Makineni ,  Steven R. King ,  Zhen Fang ,  Alexander Redkin ,  Ravishankar Iyer ,  Pavel S. Smirnov ,  Dmitry Gusev ,  Dmitri Pavlov ,  May Wu

    IPC: G06F9/30

    CPC classification number: G06F9/30076 ,  G06F1/32 ,  G06F9/30196 ,  G06F9/3822 ,  G06F9/3891

    Abstract: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.

    Abstract translation: 处理器可以用仅执行需要完全向后兼容的一些部分指令集的核来构建。 因此，在一些实施例中，可以通过提供仅执行特定指令而不是其他指令的部分核来降低功耗。 不支持的指令可以以其他更节能的方式处理，使得包括部分核心的整体处理器可以完全向后兼容。

    PACKET SWITCHING
    20.
    发明申请
    PACKET SWITCHING 审中-公开

    公开(公告)号：US20150195206A1

    公开(公告)日：2015-07-09

    申请号：US14563267

    申请日：2014-12-08

    Applicant: INTEL CORPORATION

    Inventor： Mazhar I. Memon ,  Steven R. King

    IPC: H04L12/851 ,  H04L12/863

    CPC classification number: H04L47/24 ,  H04L47/10 ,  H04L47/2433 ,  H04L47/2475 ,  H04L47/2483 ,  H04L47/32 ,  H04L47/50 ,  H04L47/6255 ,  H04L47/627 ,  H04L49/109

    Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

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