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    Vector mask driven clock gating for power efficiency of a processor
    12.
    发明授权
    Vector mask driven clock gating for power efficiency of a processor 有权

    公开(公告)号：US10133577B2

    公开(公告)日：2018-11-20

    申请号：US13997791

    申请日：2012-12-19

    Applicant: Intel Corporation

    Inventor： Jesus Corbal ,  Dennis R. Bradford ,  Jonathan C. Hall ,  Thomas D. Fletcher ,  Brian J. Hickmann ,  Dror Markovich ,  Amit Gradstein

    IPC: G06F1/32 ,  G06F9/30 ,  G06F9/38

    Abstract: A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.

    INSTRUCTION AND LOGIC TO PROVIDE VECTOR LINEAR INTERPOLATION FUNCTIONALITY
    13.
    发明申请
    INSTRUCTION AND LOGIC TO PROVIDE VECTOR LINEAR INTERPOLATION FUNCTIONALITY 有权
    指令和逻辑提供矢量线性插值功能

    公开(公告)号：US20160266902A1

    公开(公告)日：2016-09-15

    申请号：US13977736

    申请日：2011-12-16

    Applicant: Intel Corporation

    Inventor： Jesus Corbal ,  Andrew T. Forsyth ,  Lisa K. Wu ,  Thomas D. Fletcher

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3836 ,  G06F15/8053 ,  G06F17/17 ,  G06T3/4007

    Abstract: Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.

    Abstract translation: 指令和逻辑提供矢量线性插值功能。 在一些实施例中，响应于指令指定：来自一组向量寄存器的第一操作数，每个向量元素的大小，用于计算线性内插的向量元素的一部分，来自一组向量的第二操作数 寄存器和第三操作数; 执行单元分别从第一，第二和第三操作数中的对应数据字段读取向量元素的大小的第一值，第二和第三值，并计算内插值作为第一值乘以第二值减去 第二个值乘以第三个值加上第三个值。

    Systems, apparatuses, and methods for chained fused multiply add
    15.
    发明授权
    Systems, apparatuses, and methods for chained fused multiply add 有权

    公开(公告)号：US10853065B2

    公开(公告)日：2020-12-01

    申请号：US16169456

    申请日：2018-10-24

    Applicant: Intel Corporation

    Inventor： Jesus Corbal ,  Robert Valentine ,  Roman S. Dubtsov ,  Nikita A. Shustrov ,  Mark J. Charney ,  Dennis R. Bradford ,  Milind B. Girkar ,  Edward T. Grochowski ,  Thomas D. Fletcher ,  Warren E. Ferguson

    IPC: G06F9/30 ,  G06F7/544 ,  G06F7/483

    Abstract: Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand. Execution circuitry executes the decoded single instruction to perform iterations of packed fused multiply accumulate operations by multiplying packed data elements of the sources of the first type by sub-elements of the scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.

    VECTOR MASK DRIVEN CLOCK GATING FOR POWER EFFICIENCY OF A PROCESSOR
    17.
    发明申请
    VECTOR MASK DRIVEN CLOCK GATING FOR POWER EFFICIENCY OF A PROCESSOR 审中-公开
    矢量屏幕驱动时钟增益的处理器的功率效率

    公开(公告)号：US20150220345A1

    公开(公告)日：2015-08-06

    申请号：US13997791

    申请日：2012-12-19

    Applicant: INTEL CORPORATION

    Inventor： Jesus Corbal ,  Dennis R. Bradford ,  Jonathan C. Hall ,  Thomas D. Fletcher ,  Brian J. Hickmann ,  Dror Markovich ,  Amit Gradstein

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3836 ,  G06F1/3243 ,  G06F1/329 ,  G06F9/3001 ,  G06F9/30036 ,  Y02D10/152 ,  Y02D10/24

    Abstract: A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.

    Abstract translation: 处理器包括指令调度和调度（调度/调度）单元，以接收单个指令多数据（SIMD）指令，以对存储在由第一源操作数指示的存储位置中的多个数据元素执行操作。 指令调度/调度单元是基于第二源操作数来确定将不被操作以生成写入目的地操作数的结果的第一数据元素。 处理器还包括耦合到指令调度/调度单元的多个处理单元，以矢量方式处理SIMD指令的数据单元，以及耦合到指令调度/调度单元的功率管理单元，以减少第一 所述处理元件被配置为处理所述第一数据元素。

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