公开(公告)号：US20190102229A1

公开(公告)日：2019-04-04

申请号：US15721858

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Russell J. Fenger ,  Vijay Dhanraj ,  Deepak Samuel Kirubakaran ,  Srividya Ambale ,  Israel Hirsh ,  Eliezer Weissmann ,  Hisham Abu-Salah

IPC: G06F9/50

Abstract: Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.

公开(公告)号：US20190102227A1

公开(公告)日：2019-04-04

申请号：US15720222

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash Ananthakrishnan ,  Vijay Dhanraj ,  Russell Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen Gunter ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth Sistla ,  Guy Therien ,  Ankush Verma ,  Eliezer Weissmann

IPC: G06F9/50 ,  G06F9/48

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US20160371118A1

公开(公告)日：2016-12-22

申请号：US14741782

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Vijay Dhanraj ,  Abhinav R. Karhu ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F9/485 ,  G06F9/45558 ,  G06F9/5027 ,  G06F9/5077 ,  G06F2009/4557 ,  G06F2009/45575

Abstract: Apparatuses, methods and storage media associated with managing operations of a virtual machine including dynamic idling and scheduling of virtual processors on logical processors described herein. In embodiments, an apparatus may include a physical computing platform with one or more physical processors, a virtual machine manager to manage operation of virtual machines each with a priority level and with one or more virtual processors that operate on logical processor instances of the one or more physical processors, wherein the virtual machine manager tracks activities of the virtual processors that operate on a shared logical processor instance and selectively idles and schedules one or more virtual processors in view of at least the activities of the virtual processors that operate on a shared logical processor instance and the priority of the virtual machines associated with the one or more virtual processors.

Abstract translation: 与管理虚拟机的操作相关联的装置，方法和存储介质，包括本文所述的逻辑处理器上的虚拟处理器的动态空闲和调度。 在实施例中，装置可以包括具有一个或多个物理处理器的物理计算平台，虚拟机管理器，用于管理各自具有优先级的虚拟机的操作，以及一个或多个虚拟处理器，其在一个或多个物理处理器的逻辑处理器实例上操作 更多物理处理器，其中虚拟机管理器跟踪在共享逻辑处理器实例上操作的虚拟处理器的活动，并且考虑到至少在共享逻辑上操作的虚拟处理器的活动，选择性地空闲并调度一个或多个虚拟处理器 处理器实例和与一个或多个虚拟处理器相关联的虚拟机的优先级。