公开(公告)号：US10146283B2

公开(公告)日：2018-12-04

申请号：US15804020

申请日：2017-11-06

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Satish K. Damaraju ,  Yun-Han Chen ,  Ryan D. Wells ,  Inder M. Sodhi ,  Vishram Sarurkar ,  Ken Drottar ,  Ashish V. Choubal ,  Rabiul Islam

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/50

Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

公开(公告)号：US20180341305A1

公开(公告)日：2018-11-29

申请号：US16056949

申请日：2018-08-07

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Satish K. Damaraju ,  Yun-Han Chen ,  Ryan D. Wells ,  Inder M. Sodhi ,  Vishram Sarurkar ,  Ken Drottar ,  Ashish V. Choubal ,  Rabiul Islam

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F1/26 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D10/22

Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

公开(公告)号：US09223365B2

公开(公告)日：2015-12-29

申请号：US13844824

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： Ivan Herrera Mejia ,  Vishram Sarurkar ,  Vijay K. Vuppaladadium

IPC: G06F1/24 ,  G06F1/30 ,  G06F1/32

CPC classification number: G06F1/24 ,  G06F1/305 ,  G06F1/3212 ,  Y02D10/174

Abstract: A system, semiconductor device and method for providing a controlled system reset sequence with lower power consumption without dependency on fuses, PLL's and external XTAL's. A method to simplify a boot sequence by using a ring oscillator that compensates for voltage and temperature variations while also removing the dependency on parallel fuses, PLL's and external XTAL's.

Abstract translation: 一种用于提供具有较低功耗的受控系统复位序列而不依赖于保险丝，PLL和外部XTAL的系统，半导体器件和方法。 通过使用补偿电压和温度变化的环形振荡器来简化引导顺序的方法，同时也消除了对并联保险丝，PLL和外部XTAL的依赖。