公开(公告)号：US11748606B2

公开(公告)日：2023-09-05

申请号：US17317857

申请日：2021-05-11

申请人： INTEL CORPORATION

发明人： Kamal Sinha ,  Balaji Vembu ,  Eriko Nurvitadhi ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Farshad Akhbari ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Nadathur Rajagopalan Satish ,  John C. Weast ,  Mike B. MacPherson ,  Linda L. Hurd ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC分类号： G06F7/50 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06T1/20 ,  G06F9/30 ,  G06T15/00 ,  G06F15/78 ,  G06F15/76 ,  G06F1/3287 ,  G06F1/3293 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06T1/60

CPC分类号： G06N3/063 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/30014 ,  G06F9/30036 ,  G06F15/76 ,  G06F15/78 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084 ,  G06T1/20 ,  G06T15/005 ,  G06T1/60

摘要： In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：US11636831B2

公开(公告)日：2023-04-25

申请号：US17383644

申请日：2021-07-23

申请人： Intel Corporation

发明人： Sanjeev S. Jahagirdar ,  Tapan A. Ganpule ,  Anupama A. Thaploo ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC分类号： G09G5/393 ,  G09G5/399 ,  G06F13/40 ,  G09G5/02 ,  G09G5/37 ,  G09G5/34 ,  H03K19/00 ,  H03K19/08 ,  G06F3/14 ,  G09G5/36

摘要： Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

公开(公告)号：US11320886B2

公开(公告)日：2022-05-03

申请号：US17108951

申请日：2020-12-01

申请人： Intel Corporation

发明人： Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Kiran C. Veernapu ,  Eric J. Asperheim ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC分类号： G06F15/00 ,  G06F1/3234 ,  G06F9/46 ,  G06F1/329

摘要： Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200348897A1

公开(公告)日：2020-11-05

申请号：US16881262

申请日：2020-05-22

申请人： Intel Corporation

发明人： Eric J. Asperheim ,  Subramaniam M. Maiyuran ,  Kiran C. Veernapu ,  Sanjeev S. Jahagirdar ,  Balaji Vembu ,  Devan Burke ,  Philip R. Laws ,  Kamal Sinha ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Altug Koker

IPC分类号： G06F3/14 ,  G06F3/01 ,  G09G5/391 ,  G06F3/0484

摘要： In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

公开(公告)号：US20200210238A1

公开(公告)日：2020-07-02

申请号：US16726341

申请日：2019-12-24

申请人： Intel Corporation

发明人： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC分类号： G06F9/50 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/48 ,  G06F1/329

摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US10691392B2

公开(公告)日：2020-06-23

申请号：US15488758

申请日：2017-04-17

申请人： Intel Corporation

发明人： Eric J. Asperheim ,  Subramaniam M. Maiyuran ,  Kiran C. Veernapu ,  Sanjeev S. Jahagirdar ,  Balaji Vembu ,  Devan Burke ,  Philip R. Laws ,  Kamal Sinha ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Altug Koker

IPC分类号： G06F3/01 ,  G06F3/14 ,  G09G5/391 ,  G06F3/0484 ,  G09G5/00

摘要： In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

公开(公告)号：US20190265765A1

公开(公告)日：2019-08-29

申请号：US16286166

申请日：2019-02-26

申请人： Intel Corporation

发明人： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Prasoonkumar Surti ,  Kiran C. Veernapu

IPC分类号： G06F1/20 ,  G05B19/05

摘要： Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors. The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190155350A1

公开(公告)日：2019-05-23

申请号：US16251527

申请日：2019-01-18

申请人： Intel Corporation

发明人： Sandeep K. Venishetti ,  Sanjeev S. Jahagirdar ,  Srinivas Thota

IPC分类号： G06F1/26 ,  G06F1/3287 ,  G06F1/18

摘要： An apparatus includes a distribution network that includes circuitry configured to receive first power from a first voltage source and second power from a second voltage source, and to deliver power to each of a plurality of electronic circuitry blocks (ECBs), including to deliver first ECB power to a first ECB and second ECB power to a second ECB. The first ECB power includes a first portion of the first power and a first portion of the second power. The apparatus also includes power management logic to dynamically adjust the power to be provided to each ECB. Responsive to a change in a first activity level of the first ECB, the power management logic is to change the first ECB power by adjustment of the first portion of the first power and adjustment of the first portion of the second power. Other embodiments are described and claimed.

公开(公告)号：US20180307971A1

公开(公告)日：2018-10-25

申请号：US15495020

申请日：2017-04-24

申请人： Intel Corporation

发明人： Kamal Sinha ,  Balaji Vembu ,  Eriko Nurvitadhi ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Farshad Akhbari ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Nadathur Rajagopalan Satish ,  John C. Weast ,  Mike B. MacPherson ,  Linda L. Hurd ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC分类号： G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06T1/20

CPC分类号： G06N3/063 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/30014 ,  G06F9/30036 ,  G06F15/78 ,  G06N3/04 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005

摘要： In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210232204A1

公开(公告)日：2021-07-29

申请号：US17108951

申请日：2020-12-01

申请人： Intel Corporation

发明人： Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Kiran C. Veernapu ,  Eric J. Asperheim ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC分类号： G06F1/3234 ,  G06F9/46 ,  G06F1/329

摘要： Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.