公开(公告)号：US10885259B2

公开(公告)日：2021-01-05

申请号：US16557945

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Bikram Baidya ,  John A. Swanson ,  Kumara Sastry ,  Prasad N. Atkar ,  Vivek K. Singh

IPC: G06F30/00 ,  G06F30/398 ,  G06F17/18 ,  G06N5/02 ,  G06K9/62 ,  G06F30/392 ,  G06N20/00

Abstract: An improved random forest model is provided, which has been trained based on silicon data generated from tests of previously fabricated chips. An input is provided to the random forest model, the input including a feature set of a pattern within a particular chip layout, the feature set identifying geometric attributes of polygonal elements within the pattern. A result is generated by the random forest model based on the input, where the result identifies a predicted attribute of the pattern based on the silicon data, and the result is generated based at least in part on determining, within the random forest model, that geometric attributes of the pattern were included in the previously fabricated chips, where the previously fabricated chips have chip layouts are different from the particular chip layout.

公开(公告)号：US20200005451A1

公开(公告)日：2020-01-02

申请号：US16557906

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Bikram Baidya ,  Allan Gu ,  Vivek K. Singh ,  Abde Ali Hunaid Kagalwalla

IPC: G06T7/00 ,  G06F7/544

Abstract: A method includes, for each data object of a plurality of data objects, performing a measurement on a plurality of instances of the data object to generate a plurality of measurement values for the data object, and generating a distribution of the measurement values for the data object. The method further includes generating an aggregate distribution based on each of the distributions of the measurement values generated for the data objects, and scoring a first data object of the plurality of data objects based on the distribution of the measurement values for the first data object and the aggregate distribution.

公开(公告)号：US11663700B2

公开(公告)日：2023-05-30

申请号：US16457926

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： John A. Swanson ,  Vivek K. Singh ,  Kumara Sastry ,  Helen F. Parks ,  I-Tzu Chen

IPC: G06N3/126 ,  G06N20/00 ,  G06N7/01 ,  G06T5/00 ,  G06F17/18 ,  G06F18/24 ,  G06V10/762 ,  G06V10/764 ,  G06V10/40

CPC classification number: G06T5/002 ,  G06F17/18 ,  G06F18/24 ,  G06N3/126 ,  G06N7/01 ,  G06N20/00 ,  G06V10/40 ,  G06V10/762 ,  G06V10/764

Abstract: A method comprising identifying a set of target features for a plurality of data instances of an input data collection; determining feature values for the set of target features for the plurality of data instances; identifying a plurality of outlier data instances based on the determined feature values; identifying a plurality of noisy data instances from the outlier data instances based on feature values of the plurality of noisy data instances, wherein a noisy data instance is identified based on a determination that noise is present in noisy data instance; and providing an indication of the plurality of noisy data instances.

公开(公告)号：US11282189B2

公开(公告)日：2022-03-22

申请号：US16572594

申请日：2019-09-16

Applicant: Intel Corporation

Inventor： John A. Swanson ,  Kenny K. Toh ,  Kumara Sastry ,  Lillian Chang ,  Manuj Swaroop ,  Vivek K. Singh

IPC: G06T7/00

Abstract: Images are accessed representing a status in a fabrication of a semiconductor chip corresponding to a particular stage in the fabrication. Distortion is removed from the images and actual features of the semiconductor chip are extracted from the images. Synthesized ideal features of the semiconductor chip associated with completion of the particular stage in the fabrication are determined from the one or more images. The actual features are compared to the ideal features to determine whether anomalies associated with the particular stage exist in the semiconductor chip.

公开(公告)号：US20200013157A1

公开(公告)日：2020-01-09

申请号：US16572594

申请日：2019-09-16

Applicant: Intel Corporation

Inventor： John A. Swanson ,  Kenny K. Toh ,  Kumara Sastry ,  Lillian Chang ,  Manuj Swaroop ,  Vivek K. Singh

IPC: G06T7/00

Abstract: Images are accessed representing a status in a fabrication of a semiconductor chip corresponding to a particular stage in the fabrication. Distortion is removed from the images and actual features of the semiconductor chip are extracted from the images. Synthesized ideal features of the semiconductor chip associated with completion of the particular stage in the fabrication are determined from the one or more images. The actual features are compared to the ideal features to determine whether anomalies associated with the particular stage exist in the semiconductor chip

公开(公告)号：US09822470B2

公开(公告)日：2017-11-21

申请号：US13714990

申请日：2012-12-14

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Brian S. Doyle ,  Shawna M. Liff ,  Vivek K. Singh

IPC: D03D1/00 ,  H01B7/04 ,  D02G3/44 ,  D04H3/00 ,  D01D5/00 ,  D01D5/34 ,  B21C37/04 ,  B21C23/08 ,  D04H1/4266 ,  D04H1/4382

CPC classification number: D03D1/0088 ,  B21C23/08 ,  B21C37/042 ,  B21C37/047 ,  D01D5/00 ,  D01D5/34 ,  D02G3/441 ,  D04H1/4266 ,  D04H1/4382 ,  D04H3/00 ,  D10B2401/16 ,  D10B2401/18 ,  Y10T442/3057 ,  Y10T442/603

Abstract: Flexible electronically functional fibers are described that allow for the placement of electronic functionality in traditional fabrics. The fibers can be interwoven with natural fibers to produce electrically functional fabrics and devices that can retain their original appearance.