公开(公告)号：US20190006325A1

公开(公告)日：2019-01-03

申请号：US16127004

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： Weng Hong TEH ,  John S. GUZEK ,  Shan ZHONG

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/12 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L23/13

Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

公开(公告)号：US20160233166A1

公开(公告)日：2016-08-11

申请号：US14367711

申请日：2013-08-21

Applicant: Weng Hong TEH ,  John S. GUZEK ,  Robert L. SANKMAN ,  INTEL CORPORATION

Inventor： Weng Hong TEH ,  John S. GUZEK ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/563 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/8203 ,  H01L2224/82031 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/18162

Abstract: Embodiments of the present disclosure are directed towards bumpless interfaces to an embedded silicon die, in integrated circuit (IC) package assemblies. In one embodiment, a method includes forming a surrounding portion of dielectric material defining a cavity therein; placing at least one die in the cavity, the die including a contact; depositing a dielectric material on the die and the surrounding portion; etching the dielectric material to expose the contact; and depositing conductive material onto the contact. Other embodiments may he described and/or claimed.

Abstract translation: 本公开的实施例针对集成电路（IC）封装组件中的嵌入式硅管芯的无扰动接口。 在一个实施例中，一种方法包括在其中形成限定空腔的电介质材料的周围部分; 将至少一个模具放置在所述空腔中，所述模具包括接触件; 在模具和周围部分上沉积电介质材料; 蚀刻介电材料以暴露接触; 并将导电材料沉积到触点上。 他可以描述和/或要求保护其他实施例。