公开(公告)号：US20180189182A1

公开(公告)日：2018-07-05

申请号：US15394649

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Christopher B. WILKERSON ,  Zeshan A. CHISHTI

IPC: G06F12/0864 ,  G06F12/0891 ,  G06F17/30

CPC classification number: G06F12/0864 ,  G06F12/0891 ,  G06F2212/1024

Abstract: In one embodiment, aggregated write back in a direct mapped two level memory in accordance with the present description, aggregates a dirty block or other subunit of data being evicted from a near memory of a two level memory system, with other spatially co-located dirty subunits of data in a sector or other unit of data for write back to a far memory of the two level memory system. In one embodiment, dirty spatially co-located subunits are scrubbed and aggregated with one or more spatially co-located dirty subunits being evicted. In one embodiment, a write combining buffer is utilized to aggregate spatially co-located dirty subunits prior to being transferred to a far memory write buffer in a write back operation. Other aspects are described herein.

公开(公告)号：US20170371795A1

公开(公告)日：2017-12-28

申请号：US15193952

申请日：2016-06-27

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Christopher B. WILKERSON ,  Zeshan A. CHISHTI

IPC: G06F12/0873 ,  G06F12/123 ,  G06F12/0804

CPC classification number: G06F12/0873 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/124 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/608

Abstract: An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory. The memory controller also includes idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory. The memory controller is to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that an observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory.

公开(公告)号：US20250004773A1

公开(公告)日：2025-01-02

申请号：US18217428

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Zhe WANG ,  Dan BAUM ,  Venkateswara Rao MADDURI ,  Chen DAN ,  Joseph NUZMAN

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are described for prefetching data with hints. For example, one embodiment of a processor comprises: a plurality of cores to process instructions; a first core of the plurality of cores comprising: decoder circuitry to decode instructions indicating memory operations including load operations of a first type with shared data hints and load operations of a second type without shared data hints; execution circuitry to execute the instructions to perform the memory operations; data prefetch circuitry to store tracking data in a tracking data structure responsive to the memory operations, a portion of the tracking data associated with the first type of load operations; and the data prefetch circuitry to detect memory access patterns using the tracking data, the data prefetch circuitry to responsively issue one or more prefetch operations using shared data hints based, at least in part, on the portion of the tracking data associated with the first type of load operations.

公开(公告)号：US20220197642A1

公开(公告)日：2022-06-23

申请号：US17133328

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Alaa R. ALAMELDEEN ,  Christopher J. HUGHES

IPC: G06F9/30 ,  G06F12/0862 ,  H03M7/30

Abstract: A processor that includes compression instructions to compress multiple adjacent data blocks of uncompressed read-only data stored in memory into one compressed read-only data block and store the compressed read-only data block in multiple adjacent blocks in the memory is provided. During execution of an application to operate on the read-only data, one of the multiple adjacent blocks storing the compressed read-only block is read from memory, stored in a prefetch buffer and decompressed in the memory controller. In response to a subsequent request during execution of the application for an adjacent data block in the compressed read-only data block, the uncompressed adjacent block is read directly from the prefetch buffer.

公开(公告)号：US20190042145A1

公开(公告)日：2019-02-07

申请号：US15854357

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Binh PHAM ,  Christopher B. WILKERSON ,  Alaa R. ALAMELDEEN ,  Zeshan A. CHISHTI ,  Zhe WANG

IPC: G06F3/06 ,  G06F12/1027 ,  G06F12/0897

Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.