公开(公告)号：US20200226066A1

公开(公告)日：2020-07-16

申请号：US16833337

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Zeshan A. CHISHTI ,  Sanjay K. KUMAR ,  Zvika GREENFIELD ,  Philip LANTZ ,  Eshel SERLIN ,  Asaf RUBINSTEIN ,  Robert J. ROYER, JR.

IPC: G06F12/0811 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/02 ,  G06F11/30 ,  G06F1/30

Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory having a near memory and a far memory. The memory controller to maintain first and second caches. The first cache to cache pages recently accessed from the far memory. The second cache to cache addresses of pages recently accessed from the far memory. The second cache having a first level and a second level. The first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level. The memory controller comprising logic circuitry to inform system software that: a) a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory; and/or, b) a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.

公开(公告)号：US20190042145A1

公开(公告)日：2019-02-07

申请号：US15854357

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Binh PHAM ,  Christopher B. WILKERSON ,  Alaa R. ALAMELDEEN ,  Zeshan A. CHISHTI ,  Zhe WANG

IPC: G06F3/06 ,  G06F12/1027 ,  G06F12/0897

Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.

公开(公告)号：US20180285271A1

公开(公告)日：2018-10-04

申请号：US15476798

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Zvika GREENFIELD ,  Zeshan A. CHISHTI ,  Israel DIAMAND

IPC: G06F12/0831 ,  G06F12/128 ,  G06F12/0891 ,  G06F12/0868 ,  G06F12/0804 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/123

CPC classification number: G06F12/0831 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/121 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/608 ,  G06F2212/69

Abstract: Provided are an apparatus, system, and method for sparse superline removal. In response to occupancy of a replacement tracker (RT) exceeding an RT eviction watermark, an eviction process is triggered for evicting a superline from a sectored cache storing at least one superline. An eviction candidate is selected from superlines that have: 1) a sector usage below or equal to a superline low watermark and 2) an RT timestamp that is greater than a superline age watermark.

公开(公告)号：US20180285274A1

公开(公告)日：2018-10-04

申请号：US15476838

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Elvira TERAN ,  Zeshan A. CHISHTI ,  Christopher B. WILKERSON ,  Zhe WANG

IPC: G06F12/0864 ,  G06F12/0804 ,  G06F12/0873 ,  G06F13/16 ,  G06F12/02 ,  G06F12/06

Abstract: Provided are an apparatus, method, and system for just-in-time cache associativity for a cache memory having cache locations as a cache for a non-volatile memory. Data is received for a target address in the non-volatile memory to add to the cache memory. A determination is made of a direct mapped cache location in the cache memory from the a target address in the non-volatile memory. The data for the target address at an available cache location in the cache memory different from the direct mapped cache location is written in response to the direct mapped cache location storing data for another address in the non-volatile memory. The data for the target address in the direct mapped cache location is written in response to the direct mapped cache location not storing data for another address in the non-volatile memory.

公开(公告)号：US20170277633A1

公开(公告)日：2017-09-28

申请号：US15400122

申请日：2017-01-06

Applicant: Intel Corporation

Inventor： Christopher B. WILKERSON ,  Alaa R. ALAMELDEEN ,  Zhe WANG ,  Zeshan A. CHISHTI

IPC: G06F12/0804 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/0292 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/608 ,  G06F2212/651 ,  G11C8/00 ,  G11C11/56 ,  G11C16/08

Abstract: A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.

公开(公告)号：US20180188953A1

公开(公告)日：2018-07-05

申请号：US15396204

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Zeshan A. CHISHTI ,  Muthukumar P. SWAMINATHAN ,  Alaa R. ALAMELDEEN ,  Kunal A. KHOCHARE ,  Jason A. GAYMAN

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3418

Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively. A second voltage level is used to read data from read addresses that do not map to one of the first and the second level indications the first and second level data structures, respectively.

公开(公告)号：US20180188797A1

公开(公告)日：2018-07-05

申请号：US15394631

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Christopher B. WILKERSON ,  Zeshan A. CHISHTI

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F13/4282 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus is described. The apparatus includes power management logic circuitry to implement a power management scheme for a link in which a prior history of the link's idle time behavior is used to determine a first estimate of the link's power consumption while idle in a higher power state and determine a second estimate of the link's power consumption while idle in a lower power state. The first and second estimates are used to determine an idle time for the link at which the link is transitioned to the lower power state.

公开(公告)号：US20180189182A1

公开(公告)日：2018-07-05

申请号：US15394649

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Christopher B. WILKERSON ,  Zeshan A. CHISHTI

IPC: G06F12/0864 ,  G06F12/0891 ,  G06F17/30

CPC classification number: G06F12/0864 ,  G06F12/0891 ,  G06F2212/1024

Abstract: In one embodiment, aggregated write back in a direct mapped two level memory in accordance with the present description, aggregates a dirty block or other subunit of data being evicted from a near memory of a two level memory system, with other spatially co-located dirty subunits of data in a sector or other unit of data for write back to a far memory of the two level memory system. In one embodiment, dirty spatially co-located subunits are scrubbed and aggregated with one or more spatially co-located dirty subunits being evicted. In one embodiment, a write combining buffer is utilized to aggregate spatially co-located dirty subunits prior to being transferred to a far memory write buffer in a write back operation. Other aspects are described herein.

公开(公告)号：US20170371795A1

公开(公告)日：2017-12-28

申请号：US15193952

申请日：2016-06-27

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Christopher B. WILKERSON ,  Zeshan A. CHISHTI

IPC: G06F12/0873 ,  G06F12/123 ,  G06F12/0804

CPC classification number: G06F12/0873 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/124 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/608

Abstract: An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory. The memory controller also includes idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory. The memory controller is to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that an observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory.